vipinlal said:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity pid is
port(
u_out:out std_logic_vector( 15 downto 0);
e_in:in std_logic_vector(15 downto 0);
clk:in std_logic;
reset:in std_logic);
end pid;
architecture Behavioral of pid is
begin
process( clk)
variable u1: std_logic_vector(15 downto 0);
variable u_prev : std_logic_vector( 15 downto 0);
variable e_prev1: std_logic_vector( 15 downto 0);
variable e_prev2: std_logic_vector( 15 downto 0);
constant k1: std_logic_vector( 6 downto 0 ):="1101011";
constant k2:std_logic_vector( 6 downto 0):="1101000";
constant k3: std_logic_vector( 6 downto 0) :="0000010";
begin
if( clk'event and clk='1') then
if reset ='1' then
u_prev :="0000000000000000";
e_prev1:="0000000000000000";
e_prev2:="0000000000000000";
else
e_prev2:=e_prev1;
e_prev1:=e_in;
u1:= u1 + (k1*e_in)+(k2*e_prev1)+(k3*e_prev2);
end if;
end if;
u_out<=u1;
end process;
end Behavioral;
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