pic 16f18446 config bits timer0 problems

[nikouz]

Hi again
I have a problem with the configuration bits setting and timer0. Icreate an interrupt very simple one just to start learning with timers. I can say that spend a whole day zero result. Code is building and debugging with no issues but is not even getting inside the interrupt. I work on a MPLABx and XC8. Enclose all settings i have done up to now. Any help will be appreciated.

configuration bits

// PIC16F18446 Configuration Bit Settings
// 'C' source line config statements

// CONFIG1
#pragma config FEXTOSC = ECL // External Oscillator mode selection bits (EC below 500kHz; PFM set to low power)
#pragma config RSTOSC = LFINT // Power-up default value for COSC bits (LFINTOSC)
#pragma config CLKOUTEN = OFF // Clock Out Enable bit (CLKOUT function is disabled; i/o or oscillator function on OSC2)
#pragma config CSWEN = ON // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)
#pragma config FCMEN = ON // Fail-Safe Clock Monitor Enable bit (FSCM timer enabled)

// CONFIG2
#pragma config MCLRE = ON // Master Clear Enable bit (MCLR pin is Master Clear function)
#pragma config PWRTS = OFF // Power-up Timer Enable bit (PWRT disabled)
#pragma config LPBOREN = OFF // Low-Power BOR enable bit (ULPBOR disabled)
#pragma config BOREN = ON // Brown-out reset enable bits (Brown-out Reset Enabled, SBOREN bit is ignored)
#pragma config BORV = LO // Brown-out Reset Voltage Selection (Brown-out Reset Voltage (VBOR) set to 2.45V)
#pragma config ZCD = OFF // Zero-cross detect disable (Zero-cross detect circuit is disabled at POR.)
#pragma config PPS1WAY = ON // Peripheral Pin Select one-way control (The PPSLOCK bit can be cleared and set only once in software)
#pragma config STVREN = ON // Stack Overflow/Underflow Reset Enable bit (Stack Overflow or Underflow will cause a reset)

// CONFIG3
#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)
#pragma config WDTE = ON // WDT operating mode (WDT enabled regardless of sleep; SWDTEN ignored)
#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)
#pragma config WDTCCS = SC // WDT input clock selector (Software Control)

// CONFIG4
#pragma config BBSIZE = BB512 // Boot Block Size Selection bits (512 words boot block size)
#pragma config BBEN = OFF // Boot Block Enable bit (Boot Block disabled)
#pragma config SAFEN = OFF // SAF Enable bit (SAF disabled)
#pragma config WRTAPP = OFF // Application Block Write Protection bit (Application Block not write protected)
#pragma config WRTB = OFF // Boot Block Write Protection bit (Boot Block not write protected)
#pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration Register not write protected)
#pragma config WRTD = OFF // Data EEPROM write protection bit (Data EEPROM NOT write protected)
#pragma config WRTSAF = OFF // Storage Area Flash Write Protection bit (SAF not write protected)
#pragma config LVP = ON // Low Voltage Programming Enable bit (Low Voltage programming enabled. MCLR/Vpp pin function is MCLR.)

// CONFIG5
#pragma config CP = OFF // UserNVM Program memory code protection bit (UserNVM code protection disabled)
// #pragma config statements should precede project file includes.
// Use project enums instead of #define for ON and OFF.

#include <xc.h>

Thank you all.

 

[andre_luis]

At a glance, seems like you have enabled watchdog feature, but not handling it anywhere.

 

[betwixt]

Have you configured Timer0 to count internal clock cycles and what is the prescaler set to?
Are you loading a value into Timer 0 or just letting it 'roll over'?
It might be a good idea to declare 'count' as volatile although in this instance it will probably work as it is.
General point - set up the interrupt bits before enabling the global interrupts (GIE bit).

Brian.

 

[nikouz]

At a glance, seems like you have enabled watchdog feature, but not handling it anywhere.

i did the change but same

 

[nikouz]

Have you configured Timer0 to count internal clock cycles and what is the prescaler set to?
Are you loading a value into Timer 0 or just letting it 'roll over'?
It might be a good idea to declare 'count' as volatile although in this instance it will probably work as it is.
General point - set up the interrupt bits before enabling the global interrupts (GIE bit).

Brian.

Ok let me explain better is my fault. First i dont't have any project specific. I try to learn on that pic the timer0. I want something simple with no prescalers and postcalers plain lets say Fosc/4 internal clock.Lets start from the simple how to set config for internal clock. You see in 16F88 and 16F1829 is more straight. This is one is complicate now i will also try what yo suggest of course and let you know.

 

[nikouz]

Ok let me explain better is my fault. First i dont't have any project specific. I try to learn on that pic the timer0. I want something simple with no prescalers and postcalers plain lets say Fosc/4 internal clock.Lets start from the simple how to set config for internal clock. You see in 16F88 and 16F1829 is more straight. This is one is complicate now i will also try what yo suggest of course and let you know.

Table 18-1. Timer0 Clock Source Selections
T0CS Clock Source
111 CLC1_out
110 SOSC
101 MFINTOSC(500 kHz)
100 LFINTOSC
011 HFINTOSC
010 FOSC/4
001 Pin selected by T0CKIPPS (Inverted)
000 Pin selected by T0CKIPPS (Noninverted)

These are the bits for the clock source. Which is the right to have LFINTOSC low freq internal osc(31KHz)

thank you

 

[nikouz]

Hi all

Just last words for that problem to be here as reference to maybe something similar. Problem solved when i include the pic16F18446.h header file on the main.c file.

Thank you all