Jugantor
Junior Member level 2
Hi..
i have a query regarding synopsys primepower.
after calculating the power of different instances of a design...i have got the report in terms of the cells....(using "report_power -cell")
my problem is how can i map these cell-power informations into the design file (which is in verilog) ? like...a particular cell-power info. corresponds to which part of the verilog design file?
plz reply..
p.s.: if u didnt get the problem..plz let me know..i will tell u in details
my email iD... jug_nitd@yahoo.co.in
i have a query regarding synopsys primepower.
after calculating the power of different instances of a design...i have got the report in terms of the cells....(using "report_power -cell")
my problem is how can i map these cell-power informations into the design file (which is in verilog) ? like...a particular cell-power info. corresponds to which part of the verilog design file?
plz reply..
p.s.: if u didnt get the problem..plz let me know..i will tell u in details
my email iD... jug_nitd@yahoo.co.in