well dude i dunt understand ur question.. but i shall give u the design flow that i know..
MAGMA is the tools which helps in complete RTL to GDSII format design flow (MAGMA doesnt have a simulator)
Setp 1 - Design entry (HDL decide on ur language VHDL or Verilog HDL)
Step 2 - Simulation/ Synthesis - Obtain the netlist ..
Step 3 - System Partitioning -- (ASIC only)
Steps 1,2,3 is refered to as Pre layout simulation
Step 4 - Floor planning -- Floor planning involves various steps such as power padding, macro cell deciding ( soft macro, firm macro and hard macro) deciding the floor planning scheme (Flat or heirachial). Power distibution scheme (power ring,power strap or power mesh)
You have CTS -- Clock tree synthesis --> very important
Step 5 - placement - this decides the percentage of the chip being used and the percentage of chip resources which is free..
Step 6 - Routing -- interconnection between the various components which are placed in the different floors.
wirin can be done using aluminium (.18 micron tech) , copper (0.13 micron tech) or GaAs for (.09micron/90 nm tech)
typically the bottom 2 floors are taken for power scheme ( vcc and gnd specification)
as the number of floors increase the cost per floor (fabrication cost) increases drastically. and the aspect ratio also increases.. thickness of the floor also increases.. some aspects such as frinjin capacitance and de couplin capacitance shud be taken into consideration.. the resistance of the top layers would be lesser than the bottom layers.
routing is done between the standard blocks and the designed blocks through the top most layers.
Step 7 - Circuit extraction -- this is done on decidin the amount of resistive capacitance on each of the wires.. this is very important as it takes care of signal integrity.
there is no capacitance as such n the ckt.. there is only capacitance which acts as a load to regulate the amt of current flow through the wires..and there by helps to avoid conditions like Electromagnetic inteference/cross talk/reflection/transmission/signal degradation/ or other notable signal integrity issues.
the steps 4,5,6,7 are post layout simulations
here in MAGMA design automation tool.. u wud get a LEF/DEF format.. this is actually a dummy format which doesnt have any information abt the mos layers..
by importing the TSMC library ( pay and buy it) u can get another format which is the GDSII .. this has all information including the information on the mos layers, this is the file which is necessery for actualy fabrication.
the intermediate file formats for netlist and others are DB(database format - typically CDB cadence database)
all synthesis/simulations for design is first implemented on FPGA -- target device and checked for functionality and faults .. then after which final implementation of ASIC is done.. (either on fully custom or semi custom ASICs)
hope this helps you.. if u have any doubt plz do post a reply.. i shall get some clarifications
with regards,