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Philosophical placement of counter in vhdl

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apalopohapa

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Hi. In vhdl, if a fsm needed to stay in a specific state for a specific number of clock cycles (for example, 1000), and you wanted to keep track of them using a counter, would you instantiate it within the fsm's architecture or somewhere else (e.g. the datapath) ? I ask because it doesn't feel right to put it along with the datapath stuff because the 'passing data' never interacts with the counter, but putting it along with the fsm code seems weird too. It almost seems that you need datapath, fsm, and a third conceptual placeholder for 'fsm peripherals'. What do you think?
 

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For code readability, I prefer to place the counter operation in the FSM code. Don't see, what should be "weird" in this respect.

Generally, any meaningful synchronous counter construct can be expected to be minimized by the VHDL compiler to a similar hardware structure. Thus, it's mostly a matter of taste where to place the counter.
 

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