Phase Locked Loop - transistor sizing forphasedetector

[mytreyi]

Phase Locked Loop

please anybody tell me... Is it required transistor sizing when phase detector designing...iam not getting output at the PFD(iam using 0.18um cadence)...

 

[jesseyu1984918]

Phase Locked Loop

Did you apply too fast input to your logic gate? Usually for D-flip flop, you need enough set-up and hold time in order to make it latch the input, I think you could check on this.

 

[mytreyi]

very very thanq.....
i applied delay =0ns
rise time=100ps
fall time=100ps
v1=0v
v2=1.8v
pulse width=20ns
pulse period=40ns
(W/L)n=(W/L)p=240nm/180nm

 

[dick_freebird]

Try "sliding" the phases past each other looking for the
output to change behavior. At some phase offsets you
-should- see nothing happen. But you need to verify both
"early" and "late" operation.

 

[mytreyi]

transistor sizing...is it effected to the output....