please anybody tell me... Is it required transistor sizing when phase detector designing...iam not getting output at the PFD(iam using 0.18um cadence)...
Did you apply too fast input to your logic gate? Usually for D-flip flop, you need enough set-up and hold time in order to make it latch the input, I think you could check on this.
Try "sliding" the phases past each other looking for the
output to change behavior. At some phase offsets you
-should- see nothing happen. But you need to verify both
"early" and "late" operation.