Phase Frequency Detector without dead zone

How does the two inverter delay stage in Figure 6.14 on page 265 of Design of CMOS RF Integrated Circuits and Systems helps to eliminate dead zone in Phase Frequency Detector ?

The book version adapts the original version (Cell-Based Fully Integrated CMOS Frequency Synthesizers) with slight modification.

Any idea why the book version does not require the feedback signal of DOWN signal ?

The two inverters ensure that the UP and DOWN signals need to be both HIGH for atleast two inverter delays before they are reset to LOW. The two inverter delays is the time required for the current sources to turn on. If your current sources are too slow to turn on, then you use more of the inverter stages (make sure they are even).

The two inverters ensure that the UP and DOWN signals need to be both HIGH for atleast two inverter delays before they are reset to LOW.

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Is this above statement for original version since you mentioned reset signal ?

If not, how does the reset mechanism work for book version ?

How does the PFD deadzone-free circuit ensures that the **broken link removed** do not enter metastable state ?

The 2 inverters are needed to provide delays for the UP and Down current source to turn on.

We may use more even number inverters stage if needed to ensure the current sources are turn on.

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The book author told me the above. What does it mean by "delay reset to guarantee min pulse width" ?

The deadzone arises not because of metastability, but because it takes sometime for the current source to turn on. For example, in the figure above, when the switch for UP current source is closed, Vx needs to go to Vdd before the current source can reach the proper value. (When it was switched off, Vx goes to 0V). Similarly, it holds true for the DOWN current source.

When the reference and feedback clocks are exactly aligned and you have the reset pulse width exactly equal to the delay in current source turning on, then both the currents reach the final value before being turned off. Now imagine the reference and feedback edges are delayed wrt each other by 1ps. Both the current sources would have reached their final values (because of the reset pulse width), and one current source would be ON for an extra 1ps. And thus there is no deadzone.

If there was no minimum reset pulse width, then in 1ps, the current sources would not have been able to turn on properly and the loop would have not responded. This causes the deadzone.

Typically, the delay in turning on a current source > delay of a simple logic gate. It cannot reach metastability.

Typically, the delay in turning on a current source > delay of a simple logic gate. It cannot reach metastability.

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I am still not convinced on why the SR latches will NEVER enter metastable state.

When the reference and feedback clocks are exactly aligned and you have the reset pulse width exactly equal to the delay in current source turning on, then both the currents reach the final value before being turned off.

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What ? I do not understand this above statement.

Could you rephrase this sentence ?

I am still not convinced on why the SR latches will NEVER enter metastable state.

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I presume there's a certain probability and I don't see how it could be avoided in any of the shown circuits. But why you think that it will affect PFD operation? Did you analyze the output signals in case of metastability?

promach said:

What ? I do not understand this above statement.

Could you rephrase this sentence ?

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When the reference and feedback signals are exactly aligned, then the width of the UP and DOWN signals will be identical. If the total width of UP or DOWN in such a case has been made equal to the delay in turning on the current source, then both the current sources will reach their final value (the value for which you would have designed your current source), before starting to turn off again.

In any latch/flip flop, you get metastability when two clock edges come very close to each other. Here you have two external clocks: REF and FEEDBACK. The reset signal comes ONLY after BOTH UP and DOWN are active. And ideally, additional delays are inserted in the logic path as the time required to turn on a current source > delay in simple logic gates. (Why? Because current sources are designed for mismatch and their sizes end up larger than simple logic gates). Therefore, the reset signal edge is far away from REF and FEEDBACK clocks. There is therefore very low probability of metastability.

Edit: Look at the two D flip-flop variant of the PFD detector.

I do not understand how the two SR latches in the middle region works. What are those two latches for ?

Besides, what is the purpose of the 4-input NAND gate ?

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If the total width of UP or DOWN in such a case has been made equal to the delay in turning on the current source, then both the current sources will reach their final value (the value for which you would have designed your current source), before starting to turn off again.

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This is the core idea which I am still confused with. Why does PFD need total width of UP (and/or) DOWN ?

and why "**broken link removed**" ?

Therefore, the reset signal edge is far away from REF and FEEDBACK clocks. There is therefore very low probability of metastability.

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Wait, according to the original version, reset signal is connected to TWO three-input NAND gates, as well as TWO SR-latches. I am still not getting why low probability of metastability

Look at the two D flip-flop variant of the PFD detector.

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Could you point to a direct internet link instead since the wording does not lead to neat google search result ?

Someone else suggested me to study this N-state phase detector which outperforms the book version in terms of linearity, thus more suitable for fractional N loops.