Phase Detector Design for Delay Locked Loop

Status
Not open for further replies.
C

coolsaurabhsonu

Junior Member level 1
Joined
Jan 10, 2011
Messages
19
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,413
Hi All,

I have a very basic question, is the locking time of loop depends on the types Phase detector, means if i use PD using static logic (NAND gate) or PD using Dynamic logic(TSPC), which will have better smaller locking time and why(reason).

please replay.

Thanks
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…