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PFC inductor design is totally wrong?

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cupoftea

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Hi,
Do you agree, the PFC inductor in the following App Note (pg17) has been designed totally in error? They have violated the datasheet. It’s a 2 stacked 77083A7 torroid(s) from Mag-Inc. They wound it with 64 turns.

PFC App Note:

The PFC is 2500W from 230VAC input. Therefore, peak inductor current will be in excess of 15.3A.
However, 64 turns x 15.3A = 979.2
The 77083A7 torroid datasheet clearly only permits Ampere.Turns up to 800.
This is a clear violation of datasheet. Presumably they just assumed the “AL VS NI” graph continued as a straight line after NI=800? They are totally in error in making this assumption?

77083A7 datasheet:
 

A gapped ferrite, e.g. E65 or E70 in this case, will generally yeild a smaller result than iron powder, if you can keep the ripple down, the AC ripple current losses in the wire AND the core will be reduced ....
 
I don't see any problem with this inductor design. If at current peak conditions the A*T is too high, this will just implie that the effective inductance is much more lower than the inductance at 0A. Then, it can result in higher losses on the core due to the high frequency components of the current. However, in this case, it looks like the total losses in the cores are kept lower than 1W at full power. The minimum effective inductance is higher than 300uH so the current ripple is not too high in any case.
 
A gapped ferrite, e.g. E65 or E70 in this case, will generally yeild a smaller result than iron powder, if you can keep the ripple down, the AC ripple current losses in the wire AND the core will be reduced ....
Thanks, i always (maybe wrongly) assumed that getting cores gapped is very expensive? I imagine its not easy to do, as the brittle ferrtie will tend to want to crack and break etc.
--- Updated ---

The minimum effective inductance is higher than 300uH so the current ripple is not too high in any case.
Thanks, the attached is the design doc for the inductor of page 17 in the app note.
It shows inductance is down to 982nH at some 22A (assuming that the gradient of the NI vs AL graph stays as it was just up to NI=800.)
 

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  • Mag inc coeffs _koolmu 77083A7_pfc 600uH _1.zip
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I am not sure if your way to do the estimation of permeability drop is fine. I use the permeability vs DC bias coefficients.
This is the datasheet plot
1649587455623.png


Using coefficients on table
1649587525302.png


I can calculate the permeability drop.
This is my calculated curve
1649587672745.png


As you can see, it matches very well the original curve. These coeffcients are only valid for the range shown on datasheet graph. For Kool u 60, its maximum is around 130-140 Oe. For this design, the maximum magnetic field (Oe) is inside the shown range so the estimation should be good.
 

Attachments

  • 1649587609159.png
    1649587609159.png
    20.6 KB · Views: 98
Hi,
Thanks, i always (maybe wrongly) assumed that getting cores gapped is very expensive? I imagine its not easy to do, as the brittle ferrtie will tend to want to crack and break etc.
If I'm not mistaken, then due to production tolerances, all cores have to be grinded to meet precision.

If so, then adding the gap is just an adjustment during grinding and no extra process.

Klaus
 
f I'm not mistaken, then due to production tolerances, all cores have to be grinded to meet precision.

If so, then adding the gap is just an adjustment during grinding and no extra process
Yes, i must admit when ive spec'd it in the past, i didnt really care what the tol was on the pri......but assumed it was +/-10%.....With bridges, i didnt much care about the +30%/-20% ungapped tolerance.
I must admit with eg LLC resonant inductors it would be nice to have an exact known grinded AL value.
Though i confess i wouldnt bother gapping an offtheshelf gapped core.....i'd just allow the LLC converter to adjust its switching frequency to suit....and just tolerate the little bit of extra inefficiency.

The following shows poor tol for ungrinded ETD59 core sets....
...but doesnt show the tol for the gapped sets......well it does show the gap tolerance....its 0.05mm

The MDT software (kindly pointed out by FvM) shows AL = 381.2 FOR GAP = 1.5mm for ETD59 with N87 ferrite
..and AL = 372.5 FOR GAP = 1.55mm

So for 10 turns, that would be 37.25uH to 38.12uH

I spec'd some PQ cores for flybacks for equivalents from China...and they came back and had done them with custom mixed ferrite with distributed gap!...for pretty much zero-ish cost!
 
Last edited:

It does look like this App Note has possibly been put together by a contractor working for some distributor, as theyre looking to sell ICE3P chips...and can probably get some money off Infineon to put the App Note together....Distributors doing demo boards for chipmakers is actually quite common.......i was interviewed by a well known disti for such a job.........they had shelves full of demo boards that they had done for this and that.

So i am not knocking Infineon here...there chips are second to none

Also, the App Note schem shows the gate drive has not been done optimally....they have not got turn off diodes.......all Boost PFC gate drives would have turn off diodes.....they actually use the 1ED60N driver which in fact, doesnt need turn off diodes if you connect it up in the requisite way........but they havent done that....they have just connected pins 6 and 7 together.
 

Hi,
Do you agree, the PFC inductor in the following App Note (pg17) has been designed totally in error? They have violated the datasheet. It’s a 2 stacked 77083A7 torroid(s) from Mag-Inc. They wound it with 64 turns.

PFC App Note:

The PFC is 2500W from 230VAC input. Therefore, peak inductor current will be in excess of 15.3A.
However, 64 turns x 15.3A = 979.2
The 77083A7 torroid datasheet clearly only permits Ampere.Turns up to 800.
This is a clear violation of datasheet. Presumably they just assumed the “AL VS NI” graph continued as a straight line after NI=800? They are totally in error in making this assumption?

77083A7 datasheet:
 
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