LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL; -- Used For Simulation Purposes.
ENTITY some_thing IS
-- Port Declarations
END some_thing;
ARCHITECTURE blah_blah OF some_thing IS
-- Declare Component IBUFG
COMPONENT IBUFG
PORT (I : IN STD_LOGIC; O : OUT std_logic);
END COMPONENT;
-- Other Component Declarations(If Any) and Signal declarations Goes Here
BEGIN
--Usage
some_inst: ibufg PORT MAP (i => sigA, o => sigB);
--Other Code
END blah_blah;