perceiving rising or falling edge

[nakah]

hi everybody

I have a Digilent D2-SB board. There is a Xilinx XC2S200E FPGA on this board.
I want to use that one of the input pins for perceiving rising or falling edge. I tried to do but only I did this with clock input (GCLK). I am using VHDL.

How can I solve this problem?

thanks in advance...

 

[cyr]

Assuming that the pulses are slower than your main clock, store the signal in a register and compare that stored value (one clock cycle old) with the current value.

If the values are "10" or "01" you have a rising or falling edge respectively.

 

[omid219]

I suggest you consider the bouncing issue when sampling an externa data. Then follow the cyr's advice.

 

[dddhacker]

You can use the GCK0, GCK1, GCK2, GCK3 pins . These go directly to the DLLs. You can make your signal behave as a clock and use the risingedge or fallingedge function. These pins are fixed and you have to rout your signal to one of them.

 

[Ace-X]

You can use any input pin as a clock (not only GCKx) - just put global buffer (IBUFG) after this pin in your design and after that it can be used as a usual clock signal.

 

[tut]

i also faced the similar situation. i was supposed to drive clock input of a FF with a signal which is not sourced from the GCK pin. All my IBUFG were also used up owing to the usage of DLLs. So insertion of IBUF also worked fine for me. i vaguely remember, ISE gave some warning but the idea worked fine..

Maybe u can have a look @ http://www.fpga-faq.com/archives/40475.html#40498

tut..

 

[nakah]

You can use any input pin as a clock (not only GCKx) - just put global buffer (IBUFG) after this pin in your design and after that it can be used as a usual clock signal.

I am beginner in FPGA. How can I use IBUFG in vhdl?
Could you tell me?

thanks...

 

[Renjith]

I am beginner in FPGA. How can I use IBUFG in vhdl?
Could you tell me?

thanks...

"templates" inside the xilinx ise tells how to instantiate the ibufg components.
inside templates, have a look at the component instantation under VHDL and Verilog blocks.

 

[tut]

nakah wrote:

I am beginner in FPGA. How can I use IBUFG in vhdl?
Could you tell me?

thanks...

Here is the sample code segment:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

LIBRARY unisim;
USE unisim.vcomponents.ALL; -- Used For Simulation Purposes.

ENTITY some_thing IS
-- Port Declarations
END some_thing;

ARCHITECTURE blah_blah OF some_thing IS

-- Declare Component IBUFG
COMPONENT IBUFG
PORT (I : IN STD_LOGIC; O : OUT std_logic);
END COMPONENT;

-- Other Component Declarations(If Any) and Signal declarations Goes Here

BEGIN
--Usage
some_inst: ibufg PORT MAP (i => sigA, o => sigB);

--Other Code

END blah_blah;

tut..