PDK vs. Standard Cell Library

[pokemonstation]

what is pdk or gpdk

Hello,

I have a question regarding the differences between a PDK/CDK (Process/Cadence Design Kit) and a standard cell library. Sometime people use them interchangeably, but I think there are some inherent differences between these two things. Can anyone clarify this?

The reason I asked this question is because recently I began searching for a MOSIS compatible 130nm or 90nm process for Cadence to do custom IC layout. I personally used GPDK and NCSU before; they have layout/schematic/symbol views for nmos, pmos, metal1-9, vias, nwell, psub... basically components that let users to build a circuit. However, GPDK is not MOSIS compatible and NCSU does not have 130nm or 90nm processes. I recently obtained IBM cms9flp process ARM Standard Cell Library, however, I don't know how to install it with Cadence. For GPDK or NCSU, there is a "lib" folder that contains all the components and their views (for example, lib/nmos/Layout, lib/nmos/Schematic...). However, there is no such thing for the ARM Standard Cell Library I obtained. Is this one of the differences between PDk and Standard Cell Library. Can anyone explain? I am wondering if I should be looking for cms9flp IBM PDK instead of the Standard Library.

Thank you all in advanced!

Michael

 

[jbeniston]

compile cell library

Usually,

PDK is for analog designers (use with Cadence IC).
Standard cell library is for digital designers (use with tools such as Synopsys Design Compiler / Astro)

I suspect you do need to get the IBM PDK if you want to use Cadence IC.

 

[kumar_eee]

ic layout standard cell library

PDK is nothing but Process Development Kit.
DDK is Digital Design Kit.

PDK will have Pcell's, transistor models etc...

Std cell library contains all the primitive cells that are requested by the PD Engrs.

 

[pokemonstation]

pdk cdk

Thank you both for your responses!

 

[nav_vlsi]

icfb pdk

Hi,

PDK will contains data related to Foundy . like DRC / LVS / DFM & extraction rule decks.

std cell libarary consist of various view like cadence(virtuoso - schematic, layout ) , synopsys (.lib , .db) , celtic , voltagestorm , milkyway , gds2 , cdl , spice netlists etc.

Regards
Navien

 

[shashank_s_82]

ic cell library

Std cell libraries are the basic building block of any advance digital IC, they contain all the combinational & sequential digital & mixed signal cells which will be used for the creation of SOC or ASIC. These cells will be arranged & connected in an orderly & meaning ful pattern by using synthesis tools such as DC or RTL compiler, later on these cells along with other hard & soft marcos are used to create complete SOC. Normally people term .lib as Std cell but they are wrong bc/s Std lib contains gds2, lef, (timing, power area & cap info of cells in .lib syntax), milkyway data base (FRAM, CEL etc.), cdl & RC-info in extracted netlist, noise info in celtic or ccsn formatt, voltage storm views etc. these all views are used at different stages of ASIC design by different EDA tools....

Now PDK its definition varies from company to company what I know is PDK (Process Development Kit) contains info about the process for which the SOC or ASIC is been targetted, they are been even used to create even Std cells, Memories, I/O's & Analog portion typically they contains DRC, DFM, Antenna, LVS & extraction rule decks, along with SPICE models which are used during simulations. All the DRC & DFM info is been used to create P-cells (Cadence nomenclature) which are used in cadence icfb