MMario
Newbie level 1
Hello all!
As a part of project, I'm doing PCI Express simulations where topology looks like:
PCB1 (Intel)>---->connectors&cable>------>PCB2--->CEM--->Gfx card (TI).
The graphics card uses PCI Express generation 1, single lane (x1), so that what we will be using.
I'm doing this simulations in HyperLynx 8.1.1.
I have some question I hope some of you who know more, could fill in!
I have drawn schematic in HyperLynx LineSim, from Tx (Intel) to the Rx (TI).
Do I also have to also simulate from Rx to Tx? That is from the graphics card (XIO2000A) to the PCB1 (Intel ICH9).
Secondly since we are using one lane, we don't have to have two aggressor nets and this one lane as victim net?
Any other suggestions?
Thanks!
/Mario
As a part of project, I'm doing PCI Express simulations where topology looks like:
PCB1 (Intel)>---->connectors&cable>------>PCB2--->CEM--->Gfx card (TI).
The graphics card uses PCI Express generation 1, single lane (x1), so that what we will be using.
I'm doing this simulations in HyperLynx 8.1.1.
I have some question I hope some of you who know more, could fill in!
I have drawn schematic in HyperLynx LineSim, from Tx (Intel) to the Rx (TI).
Do I also have to also simulate from Rx to Tx? That is from the graphics card (XIO2000A) to the PCB1 (Intel ICH9).
Secondly since we are using one lane, we don't have to have two aggressor nets and this one lane as victim net?
Any other suggestions?
Thanks!
/Mario
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