spman
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Hi,
I have a design with PCIe and DDR3 RAM on ML605 board. I've implemented the RAM successfully and I'm currently trying to implement PCIe.
I'm confused with the computer side program! How should I send data from computer to FPGA? In the Xilinx example design, a program (PCItree) is used only for testing throughput. But I don't know how to send my data and how to direct them to the RAM. Is it possible to make DMA between the PCIe core and the RAM?
Thanks in advance.
- - - Updated - - -
Another question in regard to this topic:
What does mean each of the terms "Endpoint application" and "Root port application" ? I encountered to these in the Virtex-6 PCIe user guide.
I have a design with PCIe and DDR3 RAM on ML605 board. I've implemented the RAM successfully and I'm currently trying to implement PCIe.
I'm confused with the computer side program! How should I send data from computer to FPGA? In the Xilinx example design, a program (PCItree) is used only for testing throughput. But I don't know how to send my data and how to direct them to the RAM. Is it possible to make DMA between the PCIe core and the RAM?
Thanks in advance.
- - - Updated - - -
Another question in regard to this topic:
What does mean each of the terms "Endpoint application" and "Root port application" ? I encountered to these in the Virtex-6 PCIe user guide.