Apparently the question is referring to discontinuities caused by vias.
Additional options:
- use a signal integrity design tool to check the signal quality with actual PCB layout
- design the via padstack (e.g. by adjusting the antipad size) to match the trace impedance
- minimize number of vias used along a trace
- use backdrilling if necessary
Apparently the question is referring to discontinuities caused by vias.
Additional options:
- use a signal integrity design tool to check the signal quality with actual PCB layout
- design the via padstack (e.g. by adjusting the antipad size) to match the trace impedance
- minimize number of vias used along a trace
- use backdrilling if necessary
This question was asked to me in an interview.The Question was "What are the precautions needs to be taken when a high speed signal is routed in multiple layers,to avoid SI problems and impedance dicontonuity issues"
My answer was put vias near to the trace where it is crossing,so that return current can take that path.
This question was asked to me in an interview.The Question was "What are the precautions needs to be taken when a high speed signal is routed in multiple layers,to avoid SI problems and impedance dicontonuity issues"
My answer was put vias near to the trace where it is crossing,so that return current can take that path.
your answer seems correct. A ground stitched VIA or a stitched capacitor is required when changing reference layer or if a signal is routing in multiple layer. This is to avoid EMI issues. You also need to make sure to re-calculate trace impedance for those layers where transition is happening.