[SOLVED] PCB design(2 layer) Topology

[Chaitanya Varma D]

Hi,

I am designing a circuit board for my project. I chose to use surface mounted devices and PCB is 2 layered. I have knowledge on the basic PCB design, but i need to know some topology(placement) related aspects of the circuit design. My circuit has both analog components(like ADC and DAC which need considerable calculations while designing the board), and digital devices like FPGA and microcontroller. Can any one suggest some good examples or the books which I can go through to reduce EMI/ERC effects, and to get good knowledge on grounding schemes.

Please provide me any links or suggest books or suggest me some tips in the design.

Thanks in advance

 

[barry]

First of all, I'd use a four layer board, not two layers; you're just asking for trouble otherwise. Keep your analog and digital components separated. For ground plane, what I usually do is use a single plane and add cutouts to separate the analog and digital circuitry.

Do a google search of "PCB layout guidelines". There's plenty of information out there.

 

[KlausST]

Hi,

I often use two layer boards for high reliability industrial circuits.
It is possible. The manual routing process usually takes longer, especially when board area is limited.

I use bottom layer as Gnd.
First i decide board dimensions, where the connectors should be. Take care of high current, high frequency, high precision (low voltage drop), analog part and digital part.
With the schematic by hand (or second window) i place the most important IC at first, then with decreasing importanc the additional parts.

For example:
ADC, then supply decoupling C, Ref decoupling C, analog input C, reference circuit, analog lines, digital lines..

I like - if possible - for each GND connection a unique via. For power or high frequency GND connections use a couple of vias.
Don't mix analog and other signals on the same via.

Especially with switch mode circuits a fter place and route iprint the board and with colored pencils i draw the (HF) current paths.
One with open switch and the other with closed switch. From input capacitor to output capacitor and back via gnd plane.

Then use cutouts to keep dirty signals within a closed area.

Klaus

 

[shaiko]

Unless $$$ is the only driving aspect behind your design - keep out of 2 layers.
With 2 layers - you won't be able to follow "good engineering practices" for anything but the simplest school homework designs.

4 layers should be the minimum.

Signal
Power
Gnd
Signal

Is a common stackup.

 

[marce]

I often use two layer boards for high reliability industrial circuits.

Not for high reliability with digital, for bargain basement designs maybe, but even those these days with Signal Integrity/EMC issues at the forefront are at least 4 layers (and that is the absolute minimum). With the devices specified I would suspect that the footprints are not conductive to a double sided design. Any impedance controlled would be almost impossible if it is required (try routing a 50 ohm line on double sided...) as would proper control of signal returns and power distribution.

The master of EMC etc...
http://www.hottconsultants.com/techtips/split-gnd-plane.html
http://www.hottconsultants.com/
http://eu.wiley.com/WileyCDA/WileyTitle/productCd-0470189304.html

 

[barry]

There is no way you should be designing a board with an FPGA AND analog circuitry with only two layers. You'll never get a reliable design.

 

[KlausST]

Hi,

we develop electronics for a silicon pruducing company. The systems have 24/7 work time.
We switch up to 2500V AC and up to 6000A with rise time (10%-90%) of 500ns.
This gives a lot of noise.
The control units are on 2 layer boards. without excesive shielding cases.
Next to this we do the power measurements (U, I, P, f, cosphi) with a fullwave to fullwave stability down to 15 bits. (not resolution but precision)
Even the power measuring pcb is two layers.
We withstand all EMI and EMC measurements.
And it works now for years on more than 100 systems without problems.

But i´m somehow a pcb hand routed layout enthusiast. This needs time, but for me it´s a challenge.

The recommendations for a 4 layer or even more layers layout makes sense - although i don´t call it a "must".

If the OP wants a 2 Layer PCB, i let him do so.

Klaus

 

[barry]

If the OP wants a 2 Layer PCB, i let him do so.

I look forward to his future posts asking why his board doesn't work properly.

 

[Chaitanya Varma D]

Hi Barry,

In my design the FPGA is not attached on to the board, but there is a module TINY TIF that i am programming now. Actually it has a board all alone with pins to interface to outside. Actually my idea is to mount the FPGA module on the board by the use of jumpers pins. (It replicates a SMD to PDIP mount. )

Ofcourse the mixture of FPGA and the ANALOG makes the design dirty, but its my project constraint.

But thank you for you suggestions.

 

[barry]

Well, that's exactly not what you said in your initial post. Now maybe you have a fighting chance.

 

[shaiko]

A design that's so cost sensitive that it has to make do with a 2 layer PCB yet at the same time makes use of an FPGA instead of a dirt cheap MCU (?)

Seems like it's time for the account managing department to install fresh batteries in their calculator...

 

[FvM]

Ask any technical question at Edaboard and get a lot of suggestions how to change your whole life...

Seriously. I simply believe that the OP is doing an educational project where usage of a FPGA has been prescribed in the specification. Or wants to learn about FPGA applications in a hobby project.

Although I agree with KlausST that a two-layer PCB can work for mixed signal designs with FPGA, it's quite obvious that it requires considerably more layout skills than a standard four-layer board. It's not necessarily doomed to failure, but I would advise a beginner against it.

 

[marce]

I would love to disagree with KlausST (and for a lot of designs do) but 2 layers can be made to work, did a test board for a GPS module (with RF) that had to be 2 layers for cost reasons and it works.....But it was a pain and there were lots of compromises in the layout (GND and power distribution being 2) and the 50ohm RF tracks were a tad wide....
But I still say with todays RF polluted environment, noise and EMC requirements 4 layers should be a minimum, and many more are often required.
I do life/mission critical designs and NOT one of them would be 2 layers, they are/would be 4 or more layers.

 

[code_slave]

I would love to disagree with KlausST (and for a lot of designs do) but 2 layers can be made to work, did a test board for a GPS module (with RF) that had to be 2 layers for cost reasons and it works.....But it was a pain and there were lots of compromises in the layout (GND and power distribution being 2) and the 50ohm RF tracks were a tad wide....
But I still say with todays RF polluted environment, noise and EMC requirements 4 layers should be a minimum, and many more are often required.
I do life/mission critical designs and NOT one of them would be 2 layers, they are/would be 4 or more layers.

'Made to work' and reliable design do not belong in the same thread together.
I used to work with a guy who built absolutely loads of prototype products on two layer and they all worked, but once you got into actual production volumes >500, then things started to go badly wrong and failure rates would always climb through the roof.
The bosses loved him, his costings always came in low, it was always the manufacturing and sourcing departments that were not doing their jobs correctly ( after-all he had physical PROOF the design was good).

Just before he left he managed to build a product with an ASIC, the thing could actually desolder itself from the PCB he speced it for.

 

[marce]

Don't understand why you have quoted my post, it isn't me that's doing this board on two layers, neither is it me endorsing a two layer build, maybe you should read the thread especially #5.

 

[FlapJack]

"I used to work with a guy who built absolutely loads of prototype products on two layer and they all worked, but once you got into actual production volumes >500, then things started to go badly wrong and failure rates would always climb through the roof."

I think there is a lot to learn here. Can you give us a few tips of what kind of things go wrong with increased production.

 

[code_slave]

I think there is a lot to learn here. Can you give us a few tips of what kind of things go wrong with increased production.

Design/material tolerance is one of the biggest killers of production ( considering for a moment you are using good production methodology and genuine components)
That and shear stupidity………..

Background

Several years ago I received a good 'slapping' from a couple of directors.
A fellow director ( lead technical engineer) designed a product for a big 'shed' ( shed in the UK is a slang term in the trade for those people who run massive warehouse type arrangements) this product was a critical safety device.
He made 10 samples 5 for BSI testing 5 for his own brand of 'mil-spec' testing.

He followed the B.S.I standard to the letter(something you should NOT do) , the product was finished and my dept. happened to be dealing with the factory that was chosen to manufacture it.

A hold was put on the products production ( being part of our job), due to the 'design overheating' , I kid you not when it was found that a particular component was reaching 140 deg. C SURFACE temp. ( the BSI allowed non-specified parts of the design upto 160 deg. c, so it was deemed as in 'spec')
Another pet hate: NO 'holt-melt' adhesive being used in any sort of electrical designs. (Asian factories LOVE it… it is fast)

Conclusion
Initially 30,000 pcs went into the market. Then winter came and it was found that the 'safety device' was failing to trigger(there was a test button).
The heat was melting some hot melt adhesive, which was dripping down onto the circuit breaker contacts and gluing the safety device permanently 'closed', the weather make the glue go off faster, once the contacts were glued, it was a permanent defect.

Recall-- massive costs incurred and a year to try and make the product salable with mods.
(Factory re-work is horrendously expensive, especially full strip-downs. In China the government imposes a MONTHLY upward sliding tax on reworked goods)


Later…….
One of the directors said no one likes a smart a** you've not made any friends with this…. no but I sleep at night.

We are seeing an increase trend in 'dead people, fires, critical injuries' turning up in recent years, even in the UK it is no surprise.

 

[marce]

Why is it no surprise, I work for a bureau and don't see thing like you describe in any of the industries we work for. Everyone I work with takes pride in engineering and testing a job correctly. I also do a lot of life/mission critical designs where testing and safety are paramount. There are millions of product that do work and don't fail as well.
B.S.I ! very retro....

Production volumes do not increase or decrease any risk, getting the correct procedures, inspection and testing regimes in place is what is important.

 

[code_slave]

You must have some very 'limited' exposure to manufacturing then, because I have seen it across many areas and in many companies and big name testing agencies.
I have an interesting photo collection of when/how things go wrong, some several thousand images.
Once you get down to the grass roots level or on the shop floors it all comes out.
So much so I was asked to consider writing a book about my experiences in Asia & manufacturing.

 

[FvM]

Although interesting as such, I have difficulties to relate the problems discussed in code slave's posts to the original topic of using 2 layer PCB.

Some years ago it was pretty usual that PCBs for mass production, e.g. PC interface cards have been tediously hand-layouted as 2-layer design to cut costs. This practice found somehow an end due to increased circuit speed and IC complexity as well as EMC requirements, but rarely related to reliability problems.

Unless Chaitanya has open points left, the question should be probably marked as solved.