Without seeing your code it is very hard to tell.
The normal configuration is for the PIC to be the master and the VNC1 to be the SPI slave (in fact I seem to remember that the VNC1 can only be the slave) which means that the PIC is the device that is generating the CS signal (as well as the SCK).
Therefore, if there are glitches on the CS line then they are either coming from the PIC or there is something else on the line that is trying to drive the line. When properly configured to use the SPI interface, the VNC1 should not be driving that line itself.
As the VNC1 uses a 13-bit transfer, I assume that you are bit-banging the SPI master interface (as the PIC18F SPI hardware uses 8-bit exchanges).
What also concerns me from your picture are the clock pulses that are being generated when the CS line is low (they should be ignored but why generate them); why are the clock pulses not evenly timed (especially right at the left-hand and right-hand edges of your picture - again the VNC1 should only use the rising clock edge but this does look unusual to me), and also the glitches all through the picture on the DI line on mainly the trailing clock edge but also the leading clock edge in some cases.
All of this would seem to indicate a very noisy environment (perhaps a poor power supply???) with lots of cross-over between the SPI signals. Try looking at the signals in "analog" mode and I suspect you will see a lot of noise that is enough to trigger the 'digital' mode logic analyser into making the transitions.
Are you using a breadboard? They are notorious for high levels of capacitance (and hence coupling) between the tracks, especially when higher frequencies are involved.
The simply answer to your question is "no - it is not normal".
Susan