Passing vector parameter to Verilog-A module

[sbc]

Hi all,

I work with HSPICE2010 and have a Verilog-A module which has vector and real parameters. I am not able to pass such vector parameters from the netlist file. No problem with real parameters only.

NETLIST
=======
.hdl mylibrary.va
x1 node1 node2 mymodule realpar=12.2 vectorpar='[1,3]'

OUTPUT
=======
Undefined parameter or function definition [1,3] for vectorpar.

I have tried with/without quotes, curly braces, brackets, parenthesis,...

Any ideas?

Thanks!