`timescale 1ns/100ps
module top
(
input wire pulse_in
,input wire reset_n
,output wire pulse_out
);
reg [03:00] count, count_2;
reg pulse_1, pulse_2;
always @ (posedge pulse_in or negedge reset_n)
begin
if (~reset_n)
begin
count <= {4{1'b0}};
end
else
begin
if (count == 4'h9)
count <= {4{1'b0}};
else
count <= count + 1'b1;
end
end
always @ (posedge pulse_in or negedge reset_n)
begin
if (~reset_n)
begin
pulse_1 <= 1'b0;
end
else
begin
if (count == 4'h9)
pulse_1 <= 1'b1;
else
pulse_1 <= 1'b0;
end
end
always @ (negedge pulse_in or negedge reset_n)
begin
if (~reset_n)
begin
count_2 <= {4{1'b0}};
end
else
begin
count_2 <= count;
end
end
always @ (negedge pulse_in or negedge reset_n)
begin
if (~reset_n)
begin
pulse_2 <= 1'b0;
end
else
begin
if (count_2 == 4'h9)
pulse_2 <= 1'b1;
else
pulse_2 <= 1'b0;
end
end
assign pulse_out = ( (pulse_1) && (~pulse_2) );
endmodule