True. What you are describing is limited pin access. But if you suffer from generalized congestion problems in your design, having more discrete gates will usually not help. You would potentially increase the total wirelength.Disaggregating functions that have wide input fields, lets
the router pick from more options during placement.
Like, (2+3+2) all at min pitch is more of a "wall" than
2 here, 3 there, 2 over there with routable gaps between.
this is also true. in some libraries, cells with difficult pin access come pre-marked as dont_use by the library provider. of course, these cells tend to be very efficient, so not using them may degrade performancesome std cell library provide cell with the pins access is quite challenging for the processor, one best way is to mark these cells as dont_use during synthesis and PnR.