store configuration
Thanks for your reply. I needed those questions to think for myself.
how fast can you reconfigure the device(s)?How do you provide/store multiple configuration data or generate them on-the-fly (using host compupter, embedded processor, ...)?
-- I will be using JBITS API to modify the bitstream. so this will be generated on the fly by the host computer. The only modification to the bitstream is it has to replace certain LUTs which are connfigured as RAM with the new data.
Yes this will be generated on the fly. The challenge is to make sure that my Processing Engines (PEs) on the Fixed Logic Block are always being used. And somehow cache/pipeline my reconfiguration data on to the FPGA so its never waiting for the data on the Reconfigurable Block.
Lets say the Tc = Computation Time for the PE
and Trc = Time to reconfigure the device and have the new data available just in time/early in the Reconfigurable Block so my PE is not wasting anytime. And my bet is ( I am still working on the design ) that the Tc will be a little smaller than that of the Trc. I would know this once I have my design and my tools done. Then I will have to have an optimal algorithm in terms of scheduling Reconfiguration.
what about the configuration bandwidth and interface (e.g. SelectMap)?
--I will be doing the confgiuration via XHWIF which ispart of JBits API . Does this answer your question?
What kind of applications are targeted?
Bioinformatics. specifically sequence matching. Unfortunately, I dont have lot of big boards to use at my disposal. I have XCV300 board from Xess to work with right now. Once I get this working on this board, I will move on to bigger boards..hopefully Xilinx will be willing to donate some boards to a poor graduate Student