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Partial / Run-time reconfigurability in Altera FPGA

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pranavam

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isbn: 978-0-387-28485-9 gebraucht

Hai
I want to know whether partial or run-time reconfigurability is possible in altera fpga's ,more specifically Altera CycloneII2c20 Fpga's ..Plz help me
 

Hi pranavam,

Unfortunately the newest Altera chips do not support PR/DPR, neither the Quartus. But if you want to play with PR the better way is to go with Xilinx.

Apart from the PR/DPR support in the devices you need a software for the PR. At the moment the most advanced PR support is available from Xilinx. There are lots of products/publications and success stories about PR in Xilinx devices.

Please see this newsletter **broken link removed** and Xilinx's PR site **broken link removed**. You have to register to access to the Xilinx's PR site.

Very nice PR guide for Xilinx tool chain **broken link removed** .

good luck,
mhmhmh
 

Thanks ,thank u very much for the information...
My aim is to build a neural network processor in FPGA which is adaptable to new inputs, i.e its weights must change when new input is present..ie. implimentation of ART algorithm... Is there any other way other than this partial reconfigurability to do this.. plz help
 

Hi pranavam,

It looks like you need a memory for coefficients which can be updated from the FPGA firmware. The M4K can fit your needs. Please google for the "FPGA neural networks" and "FPGA adaptive filter". This could be useful https://www.us.design-reuse.com/articles/article5868.html

There is also the book "FPGA Implementations of Neural Networks" from Springer ( ISBN 978-0-387-28485-9 ) . Unfortunately I don't have it.

mhmhmh
 

Thanks mhmhmh..
Let me frank, I am selected for an altera FPGA design contest. Innovate india.. They send me a training board DE1 board using cycloneII2c20 FPGA. So i have to do project based on that.. I searched M4K and find it is something different. So i have to utilise this processor .Can it be done within this processor.? Does any one have the above mentioned book

FPGA Implementations of Neural Networks by springer publications


Thanking u once more

pranavam
 

The M4K is just a dual-port (DP) memory available in the EP2C20 device.

I haven't though to much about your application but I see that you could use DP mem to store your coefficients. Then you can use first port to read them out, and the second one to update them (coefficients).

If you have to use the NIOS II processor then it's even simpler - just google for "Neural Network in C".

When you are done with "Neural Network in C" you can try to accelerate it with "Custom Instructions in NIOS". **broken link removed**

By the way, what is your FPGA experience ? Have you implemented before any DSP blocks in the FPGA ?

good luck,
mhmhmh
 

I am a newbie in FPGA world.. But i am sure that i can learn it and i can complete the project. i have worked with microcontriollers specifically PIC microcontroller. I will follow your instructions and inform u my progresses.. Now i just started learning FPGA. Can u give some preliminary suggestions for a newbie.. I have only full one month do the project. Whether its feasible in one month....?
Y actual project title is "Adaptive learning neural networks implimentatioj in FPGA using high speed vedic mathematics". Vedic mathematics from india can be used to improve the multiplication and division .
Thanking once again ,
Jithin
 

If you have some experience with uC then go with NIOS. When you are done with "Neural Network in C" come back here. It should take you no more than one week.
Search Altera's website for the tutorials and user manuals.

If you don't have experience with VHDL read this "RTL Hardware Design Using VHDL" from Wiley-IEEE Press.

Arithmetics with VHDL "VHDL Math Tricks of the Trade" https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Something about DSP with FPGA "Digital Signal Processing with Field Programmable Gate Arrays" Second Edition by Uwe Meyer-Baese from Springer.

good luck,
mhmhmh
 

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