#### hassanzia

##### Junior Member level 3

Xilinx does not recognize the parameter I declared in the following task? I'm using Xilinx 14.2.

Code:

```
module CarrySelectAdder_GroupSize2(a,b,cin,sum,cout);
parameter n = 4;
parameter group_size = 2;
input [n-1:0] a,b;
input cin;
output reg [n:0] sum;
output reg cout;
reg [n:0] tempsum;
reg [n:0] tempcout;
always @ (*)
begin
RippleCarryAdder (a[group_size - 1:0],b[group_size - 1:0],cin,
tempsum[group_size - 1:0],tempcout[group_size - 1:0]);
sum = tempsum;
cout = tempcout;
end
task RippleCarryAdder;
parameter m = 2;
input [m-1:0] RCAa,RCAb;
input RCAcin;
output reg [m-1:0] RCAsum;
output reg RCAcout;
integer i;
reg [m:0] carry;
begin
carry[0] = RCAcin;
for (i=0; i<m; i=i+1)
begin
RCAsum[i] = (RCAa[i]^RCAb[i]^carry[i]);
carry[i+1] = (((RCAa[i]^RCAb[i]) & carry[i])|(RCAa[i]&RCAb[i]));
end
RCAcout = carry[m];
end
endtask
endmodule
```

the following errors occur when I try to compile the code :

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:917 - Undeclared signal <m>.

ERROR:Xst:2634 - "CarrySelectAdder_GroupSize2.v" line 54: For loop stop condition should depend on loop variable or be static.