While debugging an old design I came across the following code:
Code:
alias x : std_logic is y ( 18 ) ; -- y is a 32 bit wide std_logic_vector input port.
begin
process ( clock ) is
begin
if rising_edge ( clock ) then
if x = '1' then
some_other_signal <= a + b ;
[COLOR="#FF0000"]x <= '0'[/COLOR] ;
end if ;
end if ;
end process ;
Question:
Why does this code even compile ? To me it seems that the line marked in red cause 'x' to be driven by 2 drivers...
What am I missing here ?
I could possibly see if this wasn't std_logic_vector but rather something that had a synthesizable wired-and resolution function.
The other possibility is that the name of the alias is similar to the name of another signal and you've simply mistaken them.
The third thought is that the optimizer finds that x = 0 is always true and just ignores this code as unreachable. (or that some_other_signal is unused or always assigned to the same expression, making the multiple drivers a non-issue)