For SCL, I guess I would believe that analog methodology would be fine if used to analyze the circuit i.e to examine the input parasitics. However, for TSPC, or Pseudo-NMOS, it is rather difficult.
For example, for my the first 2 TFF, it is of Pseudo-NMOS to provide a Divide By 4 and after which I have TSPC to provide another Divide-By-4. Lets not going to why the topologies are chosen. Between my Pseudo-NMOS and TSPC, it is rather hard to optimize as one would like to have low power however with which you pay by your drop in current drive which result in the inability to drive the TSPC.
During the optimization, of my Pseudo-NMOS. I realized that I am rather buffed by how could I extract the loading of the TSPC on the Pseudo-NMOS so when I try to optimize my first 2 TFF, I would know how small of a Width can I go.
This was how my question came about.
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