Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Parasitics (Inductance and Capacitance)

Not open for further replies.


Member level 3
Nov 23, 2005
Reaction score
Trophy points
South East Asia
Activity points
I am using Cadence Virtuoso working a Divider to achieve a division ratio of 2402 to 2480 for a 2.4Ghz signal.

I came up with several different divider blocks which i wanted to connect up however I realized that many times, the earlier stages are unable to drive the sequential stages.

This leads me to wonder the following:

1. How could the input impedance and output impedance of a block be extracted?

It is because if the 2 impedances could be determined, then the driving problem could be simplified to that of providing enough current to charge a capacitative load.

Thank you.

One can calculate theoritically the i/p and op impedance
Practically u measure the total current drawn at the o/p node then Vsupply/total current gives the output impedance and u can similarly measure for the input impedance as well

I have recently designed a divide by 32 chain based on cascaded divide-by-2 stages...and did not have impedance mismatch issues.

You should make sure each stage has enough output voltage swing to drive the next stage and also if the gate voltage(bias) for the driving transistors is correct (if the output DC voltage of the previous stage is used directly).

I had a problem with the latter, as the output DC voltage of one stage was not correct for biasing the next stage and required some modification to solve the problem.

haadi20 -- The Divide By 32 which you had designed could I know the topology as I have a feeling that you are using SCL.

Yes, thats correct. I am using SCL topology for the divider.

For SCL, I guess I would believe that analog methodology would be fine if used to analyze the circuit i.e to examine the input parasitics. However, for TSPC, or Pseudo-NMOS, it is rather difficult.

For example, for my the first 2 TFF, it is of Pseudo-NMOS to provide a Divide By 4 and after which I have TSPC to provide another Divide-By-4. Lets not going to why the topologies are chosen. Between my Pseudo-NMOS and TSPC, it is rather hard to optimize as one would like to have low power however with which you pay by your drop in current drive which result in the inability to drive the TSPC.

During the optimization, of my Pseudo-NMOS. I realized that I am rather buffed by how could I extract the loading of the TSPC on the Pseudo-NMOS so when I try to optimize my first 2 TFF, I would know how small of a Width can I go.

This was how my question came about.

Not open for further replies.

Part and Inventory Search

Welcome to