parasitic delay in hspice

[kkantham]

ingold= hspice edaboard

i am calculating logical effort of FO4 inverter in 45nm technology. i got 'tow' as 4.8ps

i got 'g' as 1(normalized). but i got p as '10'(normalized) which should be 1. what should i change to get parasitic delay as 1

** logical effort-inverter: dc analysis**
.option ingold
.param vdx=1.1
.option post

***********************************************************************
* Subcircuits
***********************************************************************

.subckt inv a y vdd gnd p=300n
M1 y a gnd gnd nmos l=45n w=180n ad='.1u*180n' as='.1u*180n' pd='.2u+360n' ps='.2u+360n'
M2 y a vdd vdd pmos l=45n w='p' ad='.1u*p' as='.1u*p' pd='.2u+2*p' ps='.2u+2*p'
.ends inv


***********************************************************************
* Simulation netlist
***********************************************************************
vdd 1 0 dc 'vdx'
vin a 0 dc pulse( 0 'vdx' 0 5p 5p 1800p 2000p)
x1 a 2 1 0 inv
x2 2 3 1 0 inv
x3 3 4 1 0 inv
*x4 4 5 1 0 inv




.tran 1p 30n
.measure tpdr TRIG v(3) val='vdx/2' fall=1 TARG v(4) val='vdx/2' rise=1
.measure tpdf TRIG v(3) val='vdx/2' rise=1 TARG v(4) val='vdx/2' fall=1
.measure tpd param='(tpdr+tpdf)/2'





.OP
.probe

**library input files**
.include `45nm.inc`
.end

 

[erikl]

delay hspice

i am calculating logical effort of FO4 inverter in 45nm technology. i got 'tow' as 4.8ps

i got 'g' as 1(normalized). but i got p as '10'(normalized) which should be 1. what should i change to get parasitic delay as 1

Just 2 ideas:

• For a 45nm technology, you use relative big inverters
• The periphery pd, ps is not calculated as - in your case - 2*(0.1µ + w) but as (2*0.1µ + w), because the periphery part adjacent to the gate is not taken into account, s. **broken link removed**.