Parasitic currents and very large pseudo resistors.

[lhrodovalho]

Hello, fellow designers.

Currently, I'm dealing with the challenge of designing a ultra low highpass filter with the cut frequency below 1 Hz. That demands very large capacitors and resistors, and it's very hard to be make them inside ICs. The solution was to make pseudoresistors using MOS in subthreshold or reverse biased diodes to achieve resistances in the orders of gigaohms. I've seen many approaches like those in IEEE papers, more specifically, this one: https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&sqi=2&ved=0CCQQFjAA&url=http%3A%2F%2Fwww.ece.utah.edu%2F~harrison%2FJSSC_Jun_03.pdf&ei=t4WrUN_5A8q50QHDsYD4BA&usg=AFQjCNGx_g4c-HWGNi-_VX9l4iiMksdLbQ&sig2=DCh5pstHkeUGsmy5Sgld0Q. The simulations work very well, and the papers back them with silicon. Yet, it's hard to believe that the parallel parasitic impedance between the wires wouldn't mess with the whole concept. As far as I know, no layout extraction tool even bothers to extract interwire parasitic resistance. So, what are your opinions?

 

[dick_freebird]

If it's small signal then a gm-C filter is popular. But gm tends
to vary a lot with applied voltages so you may need to control
amplitude etc.

At such low frequencies you can pretty much neglect shunt
C and series L, I think. The shunt resistance, you'd be hard
pressed to measure with available DMMs and might need to
use picoammeter (if that's not low enough then you are in
trouble).

Using schemes like the PCB guys use (driven guard traces, etc.)
might be used. But I think this is not so necessary when the
IC traces are all encapsulated in silica.