banvetor
Junior Member level 1
pip capacitor
Hi everybody...
I've been doing some layout of analog circuits in AMS 0.35 CMOS process. I use Tanner Tools as layout editor, and I'm seeing some strange behavior when extracting the layout with parasitic capacitances.
For instance, if I try to extract just the layout of a single PIP capacitor of approx. 200fF, I get parasitic substrate capacitances of about 70fF for the lower plate (poly1) and of about 210fF (!!!) for the upper plate (poly2).
From the AMS documents, I can see that the parasitic capacitances for poly 2 are a little bit SMALLER than for poly1, so this should not be the cause. Also, the poly2 plate is smaller than the poly1 plate, which should also contribute to lower parasitic capacitance in the upper plate.
I have tried extracting with and without a NTUB layer beneath the capacitor and nothing changed.
From the references that I've read, the poly2 parasitic capacitance should be smaller. Does anyone have any ideas of what may be causing this in my layout?
Thanks,
Leo.
Hi everybody...
I've been doing some layout of analog circuits in AMS 0.35 CMOS process. I use Tanner Tools as layout editor, and I'm seeing some strange behavior when extracting the layout with parasitic capacitances.
For instance, if I try to extract just the layout of a single PIP capacitor of approx. 200fF, I get parasitic substrate capacitances of about 70fF for the lower plate (poly1) and of about 210fF (!!!) for the upper plate (poly2).
From the AMS documents, I can see that the parasitic capacitances for poly 2 are a little bit SMALLER than for poly1, so this should not be the cause. Also, the poly2 plate is smaller than the poly1 plate, which should also contribute to lower parasitic capacitance in the upper plate.
I have tried extracting with and without a NTUB layer beneath the capacitor and nothing changed.
From the references that I've read, the poly2 parasitic capacitance should be smaller. Does anyone have any ideas of what may be causing this in my layout?
Thanks,
Leo.