I've been doing some layout of analog circuits in AMS 0.35 CMOS process. I use Tanner Tools as layout editor, and I'm seeing some strange behavior when extracting the layout with parasitic capacitances.
For instance, if I try to extract just the layout of a single PIP capacitor of approx. 200fF, I get parasitic substrate capacitances of about 70fF for the lower plate (poly1) and of about 210fF (!!!) for the upper plate (poly2).
From the AMS documents, I can see that the parasitic capacitances for poly 2 are a little bit SMALLER than for poly1, so this should not be the cause. Also, the poly2 plate is smaller than the poly1 plate, which should also contribute to lower parasitic capacitance in the upper plate.
I have tried extracting with and without a NTUB layer beneath the capacitor and nothing changed.
From the references that I've read, the poly2 parasitic capacitance should be smaller. Does anyone have any ideas of what may be causing this in my layout?
For instance, if I try to extract just the layout of a single PIP capacitor of approx. 200fF, I get parasitic substrate capacitances of about 70fF for the lower plate (poly1) and of about 210fF (!!!) for the upper plate (poly2).
Could it be possible that the "parasitics" value of 210fF for the upper (poly2) plate actually represents the sum of the proper cap value + the parasitic cap value (from the upper plate to GND), i.e., e.g., cap value=200fF + parasitics=10fF ?
Could it be possible that the "parasitics" value of 210fF for the upper (poly2) plate actually represents the sum of the proper cap value + the parasitic cap value (from the upper plate to GND), i.e., e.g., cap value=200fF + parasitics=10fF ?
Hi Erikl... I thought about that too... but I couldn't see how this would be logical for the extractor to do... My capacitor is connected between two nodes of my circuit, and not to ground. The parasitic capacitances always connect from one of the nodes (lower or upper plate) to node 0.
leo_o2 said:
You must check your extracting command file. You can paste it here and others can find the reason for you.
Hi Leo... I don't know exactly what you mean with my extracting command file. In Tanner, the only config available for the extraction is the extract definition file, which I'm attaching to this message... but in this file there isn't any references to parasitic capacitances.
I forgot to mention that I'm using version 14 of Tanner Tools, but with the "Legacy Extract" add-in. I haven't found a way to include the parasitic capacitances on the "new extract", so I'm using the same extract tool as in the previous versions of tanner, that is now called "legacy extract".
Update: Actually, there is a Parasitic Extractor in Tanner 14, but it needs new configuration files from the Design-Kit... and currently the latest design-kit available for me for AMS 0.35 is for Tanner 13.1, so I'm still stuck with v13 extractor
I agree with Leo.
There must be an extraction deck (also DRC and LVS) which is used.
It sounds that extraction of CAPS is incorrectly defined.
I would recommend to ask AMS - they are good with support.
Hi everyone, I got a new setup for L-Edit from Fraunhofer and now the POLY2 capacitance seems to be less than 1fF. The POLY1 also dropped to like half of what it was.
I have a question regarding parasitics in PIP capacitors.
I am trying to extract parasitics from a single PIP capacitor in the AMS 0.35um technology.
For a 100fF capacitor (approx. 10x10 um) Assura gives me 25fF bottom plate parasitic, which agrees with the process parameters.
However, it also gives me 1fF parasitic capacitance from the top plate to the substrate.
Does anyone have any idea where this capacitance comes from?
The top plate (POLY2) is fully enclosed by the bottom plate (POLY1).
And Assura's documentation states clearly that when there is a layer between a structure and the substrate, then it acts as "shielding", meaning, Assura only calculates the coupling capacitance to the intermediate layer...
May be there's another conducting layer over (or close to) POLY2? In this case, the top plate's parasitic capacitance could be a series capacitance top-plate - higher-level-layer - GND.
Thanks erikl. I thought it might be something like that, but on the one hand I thought 3% is quite large, when there is another conductor below it and enclosing it, and on the other hand, as I said, the Assura documentation doesn't talk about fringe capacitances, but only about overlap (i.e. area) capacitances. Anyway, thanks for the useful links!
Thanks erikl. I thought it might be something like that, but on the one hand I thought 3% is quite large, when there is another conductor below it and enclosing it, and on the other hand, as I said, the Assura documentation doesn't talk about fringe capacitances, but only about overlap (i.e. area) capacitances. Anyway, thanks for the useful links!
I think erikl is right - if the bottom plate is not large enough, electric field lines from the top plate will reach the groundplane ("substrate"), and thus there will be non-zero capacitance to ground. Attached picture illustrates this effect.