Using higher metal levels reduces the parasitics to the
substrate "node" (probably not well represented as a
stiff capacitor, but that may be all you get; substrate
resistivity matters).
You ought to be able to select all of the pcapacitor
instances that are placed in the analog_extracted
(or whatever, similar; the one that is produced and
perhaps "refined" for analog / RF backannotation
has a whole mess of minuscule instances placed
with named-net connections). You might be able
to pull a layout tree on that _extracted view and
see a huge number of them in the report. Export
and sort & sift for capacitance, or dig for the nets
that you think matter. You can highlight the net
and see pcapacitor terminals light up (if you are
zoomed in sufficiently) and follow the bouncing
ball to the other side of it, to see "C to what?".
In RF processes you may also be given adjunct
pcapacitors from the transistors themselves, to
properly model the close-in interconnect driven
capacitances (esp. look at Cdg). You might be
able to gain some significant reduction there by
backing the drain metal off from the gate, you
may have to flatten and make-cell to do this but
even a couple of tenths of a micron can help a
lot, while costing not-much Rd increment in a
silicided S/D process (which almost all are).
Also be sure you check whether your PDK has
both pre-layout (where an estimate of wiring
close-in C is embedded) and post-layout (where
only the bare-device C is modeled, expecting the
parasitics to be lumped elsewhere) models set; if
so, be sure you don't use pre-layout models with
a post-layout netlist or you'll be doubly penalized.