Parameterize wire length for finding delay

[utdstu]

I want to plot length of wire versus delay curve. Is there a way I can do by hspice or cadence spectre? Right now the only option I can see is manually changing the length of wire in layout and then finding delay. Collect all the values and then plot it using excel. I want to actually find the point where delay of the wire increases exponentially with length.

 

[kemiyun]

I can think of two ways:

1- Read the process document, look for metal n resistance. Assume metal m is ground and check the cap between these two metal layers from the document. Parameterize these two with the length for a given width (you can even parameterize the number of segments you have) and run the simulation.

2- If you have abundant amount of time, write the SKILL function that generates the wire segment with length and width you specify. You can put metal resistors in the schematic view so that you have something to compare with. Then write or modify the previous function to run DRC-LVS and extract. Write the ocean script to call this SKILL function run the sim, call the function again with different length, run the sim... collect the data as comma separated file.

I might be overthinking though. It just never occurred to me to run this simulation.