Parameter (integer) to wire assignment

[bachok83]

verilog set wire to parameter

is there any way i can set values to wire from parameter value (in verilog)?

say in VHDL, i can easily use conv_std_logic_vector function.

I tried setting it right away, eg

parameter bla = 10;
wire [6:1] thewire;

assign thewire = bla+5;

that works, but synthesizer complains (warns) about truncated value as bla+5 is tracked as integer32. Is there any other way to do this?

 

[thiagu_comp]

where parameter int()

I think you can neglect the warning. The lower bits will be assigned properly.

 

[dcreddy1980]

parameter integer

parameter bla = 'd10;
wire [6:1] thewire;

assign thewire = bla + 'd5;

The above changes should remove u r warning.Let me know if it doesn't work

 

[bachok83]

erk, unfortunately that doesnt work either.

by doesnt work, i mean the synthesizer whines about it still.

I would love to ignore the warning, but i am implementing a lookup table using case, where there are 64 cases, 64 lines of warnings for just a single module.

another question is, when i use case in vhdl, synthesizer will synthesize them to few big muxes (this is proper), however case in verilog will synthesize into latches.

The reason for latches is verilog wants a variable type object to be on the left side,

reg [5:0] some;

always @ (input)
case (input)
4'b0000 : some = ..............

 

[thiagu_comp]

try this out,

parameter bla = 4'b10; //any width as u want to limit to
wire [6:1] thewire;
assign thewire = bla+3'b5;