erk, unfortunately that doesnt work either.
by doesnt work, i mean the synthesizer whines about it still.
I would love to ignore the warning, but i am implementing a lookup table using case, where there are 64 cases, 64 lines of warnings for just a single module.
another question is, when i use case in vhdl, synthesizer will synthesize them to few big muxes (this is proper), however case in verilog will synthesize into latches.
The reason for latches is verilog wants a variable type object to be on the left side,
reg [5:0] some;
always @ (input)
case (input)
4'b0000 : some = ..............