sriharsha.hs
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Dear Folks,
I am converting parallel to serial of 8 bit data using shift register.
Bu,the problem is, shift register is completely zero for all the clocks.
Please rectify.
module parallel_to_serial (clk, reset, data_in, data_out);
input clk;
input reset;
input [7:0] data_in;
output data_out;
reg [2:0] counter;
reg [7:0] shift_reg;
assign data_out = shift_reg[0];
always @(posedge clk)
begin
if (reset == 1'b0)
begin
shift_reg <= 'd0;
counter <= 'd0;
end
else
begin
shift_reg <= data_in;
if(counter <= 3'b111)
begin
shift_reg <= {shift_reg[0], shift_reg[7:1]};
counter = counter + 1'b1;
end
end
end
endmodule
I am converting parallel to serial of 8 bit data using shift register.
Bu,the problem is, shift register is completely zero for all the clocks.
Please rectify.
module parallel_to_serial (clk, reset, data_in, data_out);
input clk;
input reset;
input [7:0] data_in;
output data_out;
reg [2:0] counter;
reg [7:0] shift_reg;
assign data_out = shift_reg[0];
always @(posedge clk)
begin
if (reset == 1'b0)
begin
shift_reg <= 'd0;
counter <= 'd0;
end
else
begin
shift_reg <= data_in;
if(counter <= 3'b111)
begin
shift_reg <= {shift_reg[0], shift_reg[7:1]};
counter = counter + 1'b1;
end
end
end
endmodule