parallel to serial converter

[sriharsha.hs]

Dear Folks,

I am converting parallel to serial of 8 bit data using shift register.

Bu,the problem is, shift register is completely zero for all the clocks.

Please rectify.

module parallel_to_serial (clk, reset, data_in, data_out);

input clk;
input reset;
input [7:0] data_in;
output data_out;

reg [2:0] counter;
reg [7:0] shift_reg;

assign data_out = shift_reg[0];

always @(posedge clk)
begin
if (reset == 1'b0)
begin
shift_reg <= 'd0;
counter <= 'd0;
end
else
begin
shift_reg <= data_in;
if(counter <= 3'b111)
begin
shift_reg <= {shift_reg[0], shift_reg[7:1]};
counter = counter + 1'b1;
end
end
end
endmodule

 

[LotusElectronics]

The SN74HC165N is a neat little IC that will take an input of up to 8 parallel lines and produce a single, serial output. You can even daisychain 2+ together to add even more parallel lines. It’s a great way to increase the number of inputs on a microcontroller.

This chip works with a voltage supply anywhere in the range of 2-6VDC, and at clock frequencies of up to 29MHz.

Features:

Wide Operating Voltage Range of 2 V to 6 V
Parallel-to-Serial Data Conversion
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-μA Max ICC
±4mA Output Drive at 5 V
Low Input Current of 1 μA Max
Complementary Outputs
Direct Overriding Load (Data) Inputs
Gated Clock Inputs

 

[ads-ee]

The SN74HC165N is a neat little IC that will take an input of up to 8 parallel lines and produce a single, serial output. You can even daisychain 2+ together to add even more parallel lines. It’s a great way to increase the number of inputs on a microcontroller.

LotusElectronics, What is the point of posting to 3 separate threads with information that has NOTHING to do with each of the OP's questions? If you can't at least help the OP don't tell them something that will only confuse everyone including the OP.


That out of the way...you have a coding problem which I've highlighted in red

module parallel_to_serial (clk, reset, data_in, data_out);
	
	input			clk;
	input	 		reset;
	input [7:0] data_in;
	output		data_out;
	
	reg	[2:0] counter;
	reg	[7:0]	shift_reg;
	
	assign data_out = shift_reg[0];
				
	always @(posedge clk)
		begin
			if (reset == 1'b0)
				begin
					shift_reg <= 'd0;
					counter <= 'd0; 
				end
			else 
				begin
					[COLOR="#FF0000"]shift_reg <= data_in;[/COLOR]
					if(counter <= 3'b111) 
					begin
					shift_reg <= {shift_reg[0], shift_reg[7:1]};	
					counter = counter + 1'b1;
					end  
				end		
		end	
endmodule

You are assigning shift outside the if with data_in which then gets replaced by the {shift_reg[0], shift_reg[7:1] in the if. Because of this shift_reg never gets assigned data_in. Instead you should be assigning the data_in when the counter will roll over on the next clock.

Your comparison is using <= 7 which basically says always rotate and increment counter, which isn't what you want to do.

If you compare to counter to 7 then you'll initially shift garbage and will load actual data_in when the counter reaches 7 and it rolls over back to 0 it will output the first bit of the new data_in value. If you want it to output data_in without garbage you'll need to load on a counter of 0 each time.

Also your shift register is a rotation, is that what you really want?

regards

- - - Updated - - -

Also if you're going to build a parallel to serial shift register like this (which shifts continuously) I would add a signal that either toggles on each data load or outputs a start pulse when the first bit of a new byte is output. Either way it will allow you to determine where the byte boundaries are, which is currently indeterminate unless you output counter from the module.