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Parallel simulation of pure VHDL design

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ffllyyffllyy

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Is there any EDA vender's simulator product can support parallel simulation of pure VHDL design ?

Must take use of multicore CPU resource to reduce simulation time.

Must supported by modern CPUs, not just limited by one old CPU family.

Does the simulator need mannually partition or automatically ?

I have read Synopsys's VCS LCA release note, features such as DLP PMX PVHDL , seems unsupport, and ALP speeds up not much.
 

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