Paralelism in RTL - request for resources

[cafukarfoo]

Paralelism in RTL

Hi Sir/Madam,

Can someone give some brief explaination and example for parallelism in RTL? Thanks.

 

[Syswip]

Hi cafukarfoo,

What do you mean?
Hardware vs. Software?

Tiksan,
http://syswip.com/

 

[AdvaRes]

Re: Paralelism in RTL

Hi Sir/Madam,

Can someone give some brief explaination and example for parallelism in RTL? Thanks.

Do you mean concurrent processes ?

 

[cafukarfoo]

Re: Paralelism in RTL

Hi Advares and Syswip,

Actually i come across this parallelism in RTL idea to improve the fmax with a digital design.

That why i bring up this topic to understand more this idea?

Thanks.

 

[Syswip]

OK,

Look at this simple example:

module xor_test_seq (in1, in2, in3, in4, out1, out2);
input in1, in2, in3, in4;
output out1, out2;

assign out1 = in1 ^ in2 ^ in3;
assign out2 = out1 ^ in4;

endmodule

module xor_test_par (in1, in2, in3, in4, out1, out2);
input in1, in2, in3, in4;
output out1, out2;
wire temp1, temp2;

assign temp1 = in1 ^ in2;
assign temp2 = in3 ^ in4;

assign out1 = temp1 ^ in3;
assign out2 = temp1  ^ temp2;

endmodule

In the 1st module you have 3 XOR gates and the longest timing path is 3 * xor_delay.

In the 2nd module you have 4 XOR gates and the longest timing path is 2 * xor_delay.

So as you can see, you are improving timing but increasing area.

Please don't hesitate to ask again if this example is not what you want.

Tiksan,
http://syswip.com/

 

[cafukarfoo]

Hi Syswip,

Is there any diferent between parallelism vs pipelined concept in RTL?

Thanks.