I had designed a CMOS Power Amplifier using Cadence. Attached is my simulated PAE graph, from the graph can see that the maximum PAE is not met at Pin> 0dBm. Is it any suggestion to solve it? Thanks.
Hi,
I've changed smaller step size, but the PAE curve still didn't have much changes. But this time, my question is the x-axis (Pin), I need to get maximum PAE which stay at Pin> 0dBm.