PAE Graph

[Xxy]

Hi,

I had designed a CMOS Power Amplifier using Cadence. Attached is my simulated PAE graph, from the graph can see that the maximum PAE is not met at Pin> 0dBm. Is it any suggestion to solve it? Thanks.

 

[KlausST]

Hi,

Please follow the recommendations that memers gave at your other thread: https://www.edaboard.com/threads/how-to-make-pae-graph-smoother.397839/post-1710955

Still the step size is too coarse.

Klaus

 

[Xxy]

Hi,

Please follow the recommendations that memers gave at your other thread: https://www.edaboard.com/threads/how-to-make-pae-graph-smoother.397839/post-1710955

Still the step size is too coarse.

Klaus

Hi,
I've changed smaller step size, but the PAE curve still didn't have much changes. But this time, my question is the x-axis (Pin), I need to get maximum PAE which stay at Pin> 0dBm.

 

[KlausST]

Hi,

I've changed smaller step size

show us what you did.

We just see the curve consisting of maybe 7 points. Surely not enough..

Klaus