Packaging and pin assignment

[kingslayer]

Dear all,

I have a serious doubt on the way pins are assigned in a given design. In any processor datasheet, you can find a section describing the package (geometry, type...) and a section describing the signals of the processor design. I guess these signals are the "top-level" one, i.e. those that have to be connected to the "outside world" (off the package). However, what is not clear to me is if these signals have 1:1 correspondance to package pins or not. Could anyone please guide me through this?

Thanks in advance
Best regards

 

[marce]

Give us a device to use as an example please.
All data sheets for micros, FPGAs etc will have a pin assignment section that list the signals on every pin, these are the signals that interface with the outside world, no other signals will be referenced, only those that have a corresponding pin.
https://ww1.microchip.com/downloads/en/DeviceDoc/61156F.pdf
in the above data sheet there are pin diagrams pages 7-19 and pin lists pages 20-27.
As can be seen these relate a signal name directly to a physical pin, one caveat is that often pins can be used for more than one fuction depending on how the chip is configured. Thus you will see pin signal names such as:
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
this shows 6 functions that this pin could be used for.
So when doing the schematic symbol you could have a generic symbol with all pin name options listed, or for a specific configeration of the device, a symbol that shows the actual pin signals for that configuration only (much clearer).

 

[kingslayer]

Dear marce,

thanks for your clarification, this is the answer I was searching for I was actually looking at Intel processors, and I realized they give pin and signals list as the example you provided.

This leads to another question, however: when one refers to "pin count constraints" (like in the ITRS roadmap), does this pin count relate to package?

Thanks again
Cheers