Package and Testing of LDO

Hi All,

I've just taped-out an LDO, and I'm going to package and test the LDO soon. I have several doubts about my subsequent work. I greatly appreciate your kind suggestions and advises.

Before I raise my questions, please first have a glance of some specifications of the LDO,

Input voltage:1.2V
Output voltage:1V
Max loading current: 200mA
Output capacitor: ~uF
Primary measurement parameters: PSRR, transient response, etc.

Below are my doubts/questions:

1. What type of package should I choose, (DIP or QFN or others)? It seems that the long bonding wire of DIP and the resultant parasitic inductance may degrade the performance of the LDO.
2. Should I solder the chip to the PCB (though expensive, the cost is not a big issue for my project) or should I use a socket? It seems that the socket brings high parasitic inductance. However, if I choose to solder the chip to the PCB, I'm afraid that the thermal issue may damage/stress my chip.
3. What kind of circuit should I adopt to emulate the loading, (resistor or current source or others)?
4. Any rule-of-thumb for the pertinent PCB design (e.g., the placement of the element, etc.)?

Looking forward to your reply.

Thank you in advance.

My suggestions:

1. What type of package should I choose, (DIP or QFN or others)? It seems that the long bonding wire of DIP and the resultant parasitic inductance may degrade the performance of the LDO.

I would recommend SOT. Very easy to scoop and goop and it is a standard package across the industry (3 5 and 6 pin varieties)
2. Should I solder the chip to the PCB (though expensive, the cost is not a big issue for my project) or should I use a socket? It seems that the socket brings high parasitic inductance. However, if I choose to solder the chip to the PCB, I'm afraid that the thermal issue may damage/stress my chip.

Another thing to consider is thermal considerations. If you pick a QFN or other package with a thermal pad you will heat up much faster without a soldered connection to PCB

3. What kind of circuit should I adopt to emulate the loading, (resistor or current source or others)?

I always recommend passive loads (resistors). Active loads act funny with some LDO in my experience

4. Any rule-of-thumb for the pertinent PCB design (e.g., the placement of the element, etc.)?

I'd check app notes for major companies such as TI, National, etc and see how they layout their LDO's. You'll want your caps to be as close to the LDO as possible obviously.