Overriding record type generic in VHDL

[PercyCuted]

Help !

I am working on a project in which MANY models have been written with VHDL record type generics (which probably seemed like a good idea at the time), but trying to change those generics for a different set of conditions is proving to be rather troublesome
eg.

package model_pg is
    type spec_type is record
        min : real;
        typ : real;
        max : real;
    end record;
end package model_pkg;
...
package model_param_pkg is
    constant VDD_C  : spec_type := (2.80, 3.70, 4.50);
end package;
...
entity block_a is
    generic (VDD_G : spec_type := VDD_C);
...

entity top is
...
architecture rtl of top is
begin
    block_a_i : top_lib.block_a

It appears that record types can not be overridden on the vsim/vopt command line with the usual -Ggeneric_name=value format, neither can an in individual field of the record be thus accessed (Modelsim)

Changing it with a configuration statement also seems to be problematic, because all components using these generics are instantiated with the format :
inst_name : entity lib_name.entity_name(arch_name), and it seems that that a configuration statement can not reference these instances, because they do not have a component name (the instantiation is in effect a hard-wired configuration)

I considered using a package configured with generics (from VHDL-2008), but this also does not seem to help, as I can't see a way of overriding the generics in a package either.

I want to be able to change the generics for some simulations, but not others, and while I could duplicate the package, and then compile/simulate twice, I really don't want to do that (does not fit in well with our regression flow)

Running out of ideas, so all contributions gratefully received !