[SOLVED] override default generic value in HDL Designer tool

[rakeshk.r]

HI, I have a component 'test1' which consist of only 2 instances of demux. The default width of demux port is set to 32 using 'Generic' statement (you can have a look at the code below).

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY demux IS
   GENERIC( width : positive := 32 );
   PORT( 
      datain : IN     signed (width-1 DOWNTO 0);
      sel    : IN     std_logic;
      out0   : OUT    signed (width-1 DOWNTO 0);
      out1   : OUT    signed (width-1 DOWNTO 0)
   );

-- Declarations

END demux ;

--
ARCHITECTURE logic OF demux IS
BEGIN
demuxlogic:process(datain,sel)
begin
case sel is
    when '0' => out0 <= datain; out1 <= (others=>'0'); 
    when '1' => out1 <= datain; out0 <= (others=>'0'); 
    when others => out0 <= (others=>'0');  out1 <= (others=>'0');   
end case; 
End process;   
END ARCHITECTURE logic;

Now I override this default value "32" to 16 for one the instances(U_0) using their object properties as shown in pic1 below.



Now the test1 struct has a generic table where i need to specify width's default value and I have done it as shown in pic2 below.



Now I compile and simulate the test1 component, So the code for interconnections in 'test1' component is generated by HDL designer tool itself and i have pasted it below (just for reference).

-- Generated by Mentor Graphics' HDL Designer(TM) 2010.2a (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY test1 IS
   GENERIC( 
      width : positive := 32
   );
   PORT( 
      datain  : IN     signed (width-1 DOWNTO 0);
      datain1 : IN     signed (width-1 DOWNTO 0);
      sel     : IN     std_logic;
      out0    : OUT    signed (width-1 DOWNTO 0);
      out1    : OUT    signed (width-1 DOWNTO 0);
      out2    : OUT    signed (width-1 DOWNTO 0);
      out3    : OUT    signed (width-1 DOWNTO 0)
   );

-- Declarations

END test1 ;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

LIBRARY project_pf_lib;

ARCHITECTURE struct OF test1 IS

   -- Architecture declarations

   -- Internal signal declarations


   -- Component Declarations
   COMPONENT demux
   GENERIC (
      width : positive := 32
   );
   PORT (
      datain : IN     signed (width-1 DOWNTO 0);
      sel    : IN     std_logic ;
      out0   : OUT    signed (width-1 DOWNTO 0);
      out1   : OUT    signed (width-1 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : demux USE ENTITY project_pf_lib.demux;
   -- pragma synthesis_on


BEGIN

   -- Instance port mappings.
   U_0 : demux
      GENERIC MAP (
         width => 16
      )
      PORT MAP (
         datain => datain,
         sel    => sel,
         out0   => out0,
         out1   => out1
      );
   U_2 : demux
      GENERIC MAP (
         width => 32
      )
      PORT MAP (
         datain => datain1,
         sel    => sel,
         out0   => out2,
         out1   => out3
      );

END struct;

Now I get error in modelsim: ** Fatal: (vsim-3348) Port size (16) does not match actual size (32) for port '/test1/U_0/datain'.
Time: 0 ns Iteration: 0 Instance: /test1/U_0 File: /edu/../project_pf_lib/hdl/demux_logic.vhd Line: 17
I don't know why the value 16 is not taken into account and where am I going wrong ? I want to know how generics are handled for the instances of a component in HDL designer tool. I don't think it is more of a logic problem. I feel one who has good experience in Mentor Graphics HDL designer might help me better. Thank you.

 

[TrickyDicky]

The problem is at the test1 level. The datain1 signal in 32 bits wide, but the port on the demux is 16 bits because you set the generic to 16. The the value 16 is taken into account, but at the top level you assigned datain1 and datain2 to be the same size.

I see two ways to fix it:
1. Have two generics at the top level: width_demux1 and width_demux2, and size datain1 and 2 appropriatly. (probably the preferable choice)
2. Have this on the demux1 port map:

dataIn => datain(15 downto 0)

2 is not preferable as you need to manually change the word slicing every time you change the generic size.