lamoun
Member level 5
Hello guys,
I am designing a 6bit / 1.7Ghz Flash ADC.
To get the SFDR / SNR ect, I use the spectrum function with rectangle window. I am using coherent sampling and I strobe the transient data at the clock frequency. I also run a DFT and crosschecked that the function works as it is supposed to.
The problem is that I am getting over-optimistic results for my circuit.
Here is a DFT with 64bins
And one with 4096 points
I undestand why SFDR increases and SNR decreases varying the DFT points, but the values for SNR /SINAD/ENOB seems over-optimistic
I run a simulation with an Ideal 8bit ADC (verilog) and got the following results proving that the spectrum function works well.
64 points
4096 points
So why am I getting this results?
Should I increase the resolution (reltol ect)?
Define a smaller maxstep for the transient?
Or should I just run my sims with montecarlo so the offset are taken in account?
*Can someone change the title to "Over-optimistic ADC SNR results"?
I am designing a 6bit / 1.7Ghz Flash ADC.
To get the SFDR / SNR ect, I use the spectrum function with rectangle window. I am using coherent sampling and I strobe the transient data at the clock frequency. I also run a DFT and crosschecked that the function works as it is supposed to.
The problem is that I am getting over-optimistic results for my circuit.
Here is a DFT with 64bins
And one with 4096 points
I undestand why SFDR increases and SNR decreases varying the DFT points, but the values for SNR /SINAD/ENOB seems over-optimistic
I run a simulation with an Ideal 8bit ADC (verilog) and got the following results proving that the spectrum function works well.
64 points
4096 points
So why am I getting this results?
Should I increase the resolution (reltol ect)?
Define a smaller maxstep for the transient?
Or should I just run my sims with montecarlo so the offset are taken in account?
*Can someone change the title to "Over-optimistic ADC SNR results"?
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