output width trouble in Vhdl programming

[knightnoor]

Hi,

I am a trainee and has been assigned the work to make a program in VHDL and have to run it in Xilinx ise ds.
My program is like i have an architecture in which we have subtractor,multiplier,adder each 4 bit two input...now the output of each component is going into a multiplexer...and i have to collect the final output from multiplexer only...now my problem is that...
adder have 5 bit output..
multiplier have 8 bit output...
subtractor have 4 bit output...
now if i take the output of multiplexer to be 8 bit...
then when the selector of mux take adder or subtractor as output then the with of the out put is 5 bit and 4 bit respectively which is less then 8 bit....
In this case what should i do as the width of output will be 8 bit in case of multiplier as input to mux(if selector choose output of multiplier which is as input to mux..the selected output from mux)...
now as obvious synthesis is giving error now plz tell me what should i do in this case...how get rid of this error.

 

[shnain]

Hello,

The 3 inputs of the MUX should be alligned to 8 bits, by filling with zeros the unsed MSbits (Adder and subtractor outputs), this will not change the operation result and you will have no issue !

BR.

 

[FvM]

this will not change the operation result

depends on, sign extension would be expected for signed results.

 

[shnain]

Yes, you are right !

If signed numbers are managed you will need to extend the MSB value (bit 3 in case of substractor, and bit 4 in case of adder) to the remaining unsed bits !

Thanks Fvm !