Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Output voltage not stable - What is compensation with respect to DC-DC (buck converter)?

Status
Not open for further replies.

FreshmanNewbie

Full Member level 6
Joined
May 10, 2020
Messages
363
Helped
0
Reputation
0
Reaction score
2
Trophy points
18
Activity points
3,625
I'm using this IC - Link

enter image description here
The schematic has a saw tooth output voltage. The MIC2103 datasheet does not describe the internal compensation used - it is only shown as a box [Compensation].
I want to understand what is this compensation box and if possible can someone explain the Type II compensation or Type III compensation in just simple terms? I read it on the internet, but not getting enough clarity.
enter image description here
The mean output voltage rises with increased load. Why is this? Please explain
 

Hi,

the shown waveform looks like a "no load condition". Show the waveform with about 10% of nominal load current.

The "non continous operation" may also be the result of a non optimal PCB layout.
--> show your PCB layout

****
--> Tell us where exactly you connected the scope probe (2 connections)

****
The mean output voltage rises with increased load. Why is this? Please explain
This often also is a problem of non optimal PCB layout


Klaus
 
Hi,

the shown waveform looks like a "no load condition". Show the waveform with about 10% of nominal load current.

The "non continous operation" may also be the result of a non optimal PCB layout.
--> show your PCB layout

****
--> Tell us where exactly you connected the scope probe (2 connections)

****

This often also is a problem of non optimal PCB layout


Klaus
Thank you for your answer. Could you tell why would the output voltage increase with increased load due to improper PCB layout? What layout aspect do you suspect that might be the cause for this?
 

Hi,
Thank you for your answer. Could you tell why would the output voltage increase with increased load due to improper PCB layout?

Ground bouce. Either DC (resistive) or AC (impedance, switching pulses)

Thus you need to know about the GND currents (DC and pulses), where they flow, where they have impact on circuit function.
* simplest way: a solid copper plane, no cuts, no other traces.
* more advanced: add cuts do divide sensitive GND from high current GND
* expert: implement other traces in this layer to reduce layer count .. while maintaining performance.

* not recommended: copper pour between random (position) traces.

Klaus
 
That looks like subharmonic oscillation (alternating fat / narrow
pulses) and this is common in current mode control needing
"slope compensation" to prevent - it is not "classic control
loop instability".

If the behavior is seen at duty setpoint > 50% but not below, this is
confirmation that it's the usual current mode control issue wanting
the usual fix. Whether you are given access in the "mystery
compensation block", I guess you'd have to read up.

On the other hand I have also seen unfortunate layout choices
(including chip pin assignments) cause similar problems right
around 50% duty, one bang-bang pin pushing / pulling on a
neighbor that was a sensitive part of the current sense that
ends up setting true pulse width. Where the "off" edge just
happens to coincide with the current-threshold decision,
you can get bistable behavior. But about a much more
specific alignment-point.
 

Attachments

  • 05-Technical-Paper-Current-Mode-Control.pdf
    119.7 KB · Views: 101
Type 2 is PI control
Type 3 is PID control

To see PI and PID control, read the first 40 pages of owen bishops book called "Undertsanding electronics control systems"



IT GIVES IT REALLY SIMPLIFIED, AND DOESNT TAKE LONG TO READ, AS ITS A frenndly book...sorry about my capitals

It looks liek the 2103 is using the fets rdson to measure the current...is that the case?...did you select a fet with correct rdson?
Also, you shoudl really use a schottky in paralell with the low side fet.
Series gate resistors also help it be less noisy.

MIC2103
 
Last edited:
Looks exactly like data sheet - at no load:

1662090173046.png

--- Updated ---

p.s. your BAT46 diode is not rated for higher Vin+Vout, it will go bang for Vin + Vout > 40V
 
I'm using this IC - Link

enter image description here
The schematic has a saw tooth output voltage. The MIC2103 datasheet does not describe the internal compensation used - it is only shown as a box [Compensation].
I want to understand what is this compensation box and if possible can someone explain the Type II compensation or Type III compensation in just simple terms? I read it on the internet, but not getting enough clarity.
enter image description here
The mean output voltage rises with increased load. Why is this? Please explain
EDITS:

Input voltage range: 24V to 48V. Changing the load current from 0.38A to 1.018A increases the mean output voltage from 12.779V to 13.26V. The supply should be producing 12.5V.
 

Hi,

Not much new information.

From the values I see about 0.5V drift ... with the feedback ratio of about 30:1 a ground bounce of about 15mV could cause the problem.
Only the PCB layout can give more insight.

Btw: your schematic shows "kelvin connection". Usually then the picture should show where exactly you designed the kelvin connections.
In your case it's expected the kelvin connections to be exactly at R603 .... but the picture shows them sonewhere else.

Klaus
 

The vout rise with load , at first look, sounds like high PCB trace resistance in the go and/or return.
If you wont show the layout, do you have a ground plane. How thick is your power trace?
 

Try putting a big 'lytic cap across C614....Steady things up on that output.
Eg try 100uF 16V or so.

Also, remove the bottom fet, and put a schottky diode in its place.

Also try remove R606.

Also, is it driving the fets with a regular stream of gate drive pulses?....you can easily see this by scoping the switching node if you want.......you shoudl see regular , equal time length pulses....maybe at low load it will be in skip cycle or burst mode...but when loaded up a bit, it shoudl be a constant stream of regular pulses....if not then its unstable and woudl explain your situation a bit.
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top