ku637
Advanced Member level 4
Hi i was going through i486SX processor datasheet,
They are specifying terms like Output Valid delay timing and Maximum Float delay timing.
Im new to microprocessor/FPGA/CPLD designs.
I just wanted to know what exactly these terms mean?
Im just writing below that it might mean..can some body please clarify?
Output Valid delay-Your output will be valid after the CLK edge after the specified time?
Float Delay- The bus will return /released to float state after the CLK edge after the specified time?
How this will be impacting in the design? Will it create signal integrity issues?
Thanks for any help,
They are specifying terms like Output Valid delay timing and Maximum Float delay timing.
Im new to microprocessor/FPGA/CPLD designs.
I just wanted to know what exactly these terms mean?
Im just writing below that it might mean..can some body please clarify?
Output Valid delay-Your output will be valid after the CLK edge after the specified time?
Float Delay- The bus will return /released to float state after the CLK edge after the specified time?
How this will be impacting in the design? Will it create signal integrity issues?
Thanks for any help,