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Output stage of a comparator

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suhas_shiv

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I have designed a comparator. The output stage is made up of a pmos and nmos transistors (just like in an opamp output stage). The nmos is in triode region and I believe that is how it should be when the pmos is in saturation. Just wanted to know if anyone thinks if both of them should be in saturation.

Thanks
 

Davood Amerion

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i think NMOS and PMOS can working in triode and saturation without any problem.
This situation used in rail to rail (MOSFET) op-amps.

you can see :TLC272
(it isnt rail to rail but include negative rail)

In this example N4 operate in both regions (triode and saturation)
 

Syukri

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my problem is...i've designed a hysterisis comparator., two stage comparator and latch comparator.

The circuit is working but the voltage to indicate 0 is 0V and 1 is 0.5V.

This is too small. Ive try to enlarge the width but still didnt give much effect.

When i check most of the transistor is at linear or cutoff region. How to saturate them?

Can anyone give the idea of what to do....to increase it up to 3.3 volt.

I'll prefer a latch comparator.

Thanks is advance.
 

paulux

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Do you want to enlarge the hystersis window or unbalance the input of the comparator in the jpg file?
 

suria3

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When dealing with comparator design, that is common for your output stages devices to be in saturation or triode region as the output either go high or low.
 

amic

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suria3 said:
When dealing with comparator design, that is common for your output stages devices to be in saturation or triode region as the output either go high or low.

definately, but what about when common mode signal is given to input with +/- inputs same. what should be the output stage condition ? Should output be Vdd/2 ?
My question pertains to 2 stage comparator with 2nd gain stage of opamp as output stage and output unloaded.
 

suria3

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amic said:
suria3 said:
When dealing with comparator design, that is common for your output stages devices to be in saturation or triode region as the output either go high or low.

definately, but what about when common mode signal is given to input with +/- inputs same. what should be the output stage condition ? Should output be Vdd/2 ?
My question pertains to 2 stage comparator with 2nd gain stage of opamp as output stage and output unloaded.

Yes, the output stage to be in saturation. The output stage dc value will be somewhere in between the 2 output MOS transistor by keeping them in saturation.
 

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