output signal as input (feedback) in verilog

[jadedfox]

feedback input

In verilog, how can we giv output signal as input(feedback).. like in case of a digital pll output of pll is fed back as input...
I think the synthesis tool gives a warning as "combinatorial loop.."
how to model it without any warning?

 

[lordsathish]

Re: feedback input

I'm not sure whether this will work.
Try using inout.
Also make it in to a sub module and while you instantiate in higher level module try to feedback the output to the input.

 

[jadedfox]

Re: feedback input

no,, it did't help...
can any one suggest any other way of doing it....[/b]

 

[thiagu_comp]

Re: feedback input

Connect output to feedback input with a buffer to avoid timing issues.

 

[haneet]

Re: feedback input

you can try by giving the output to a reg and this is connected to the output and the input port.

i am not sure.. try doing this...

haneet

 

[jadedfox]

Re: feedback input

Connect output to feedback input with a buffer to avoid timing issues.

I did it as you said but it's still giving me warning..
I need to have that combinatorial loop in my design, will it cause any simulation issues..
anyways here is how i did--

module adpll ( ref_in, en, rst_n, dco_out );
    input ref_in;
    input en, rst_n;
    output dco_out;
	 wire fed_in;
	 wire up_n;						
	 wire dn_n;
	 wire [7:0] DCO_n;
	
	 buf bf1( in1, dco_out);
	 
	 and an_ck (clk, en, ref_in);
	 
	 div_10 DV12( .out(fed_in), .in(in1), .enable(en) );
	 pfd PD1 ( .u1(ref_in), .u2(fed_in), .up(up_n), .dn(dn_n) );
	 controller CNTRL ( .reset(rst_n), .clk(clk), .up(up_n), .dn(dn_n), .DCO_CONTRL(DCO_n) );
	 dig_cntrl_osc DCO2 ( .enable(en), .DCO_OUT(dco_out), .DCO_CONTRL(DCO_n) );

endmodule

Added after 2 hours 8 minutes:

any 1 help me get a solution..

 

[dcreddy1980]

feedback input

if you can afford a extra input pin, make "in1" as i/p pin and connect the o/p dco_out to in1 with a buffer outside this module. Then this module can done with p&R and where as on top of it, you can full custom layout to put that buffer

 

[jadedfox]

Re: feedback input

if you can afford a extra input pin, make "in1" as i/p pin and connect the o/p dco_out to in1 with a buffer outside this module. Then this module can done with p&R and where as on top of it, you can full custom layout to put that buffer

thnx fr d reply...
ya i ll try that...

but can u explain the last line that u wrote.
btw i'm doing this on a fpga chip...
so i ll not be doing P & R

 

[shitansh]

Re: feedback input

Connect output to feedback input with a buffer to avoid timing issues.

I did it as you said but it's still giving me warning..
I need to have that combinatorial loop in my design, will it cause any simulation issues..
anyways here is how i did--

module adpll ( ref_in, en, rst_n, dco_out );
    input ref_in;
    input en, rst_n;
    output dco_out;
	 wire fed_in;
	 wire up_n;						
	 wire dn_n;
	 wire [7:0] DCO_n;
	
	 buf bf1( in1, dco_out);
	 
	 and an_ck (clk, en, ref_in);
	 
	 div_10 DV12( .out(fed_in), .in(in1), .enable(en) );
	 pfd PD1 ( .u1(ref_in), .u2(fed_in), .up(up_n), .dn(dn_n) );
	 controller CNTRL ( .reset(rst_n), .clk(clk), .up(up_n), .dn(dn_n), .DCO_CONTRL(DCO_n) );
	 dig_cntrl_osc DCO2 ( .enable(en), .DCO_OUT(dco_out), .DCO_CONTRL(DCO_n) );

endmodule

Added after 2 hours 8 minutes:

any 1 help me get a solution..

Which signal you want to use as feedback.
By using continuous assignment i dont think synthesis tool gives any warning like "combinational bloks". if you gets this kind of warning then it is due to input signal logic.

here it may be due to in signal in module div_10 so check the logic for in signal. I think no need to use buffer for dco_out.

HTH,
--
Shitansh Vaghela

 

[jadedfox]

Re: feedback input

Which signal you want to use as feedback.
By using continuous assignment i dont think synthesis tool gives any warning like "combinational bloks". if you gets this kind of warning then it is due to input signal logic.

here it may be due to in signal in module div_10 so check the logic for in signal. I think no need to use buffer for dco_out.

HTH,
--
Shitansh Vaghela

thnx for replying,, i'm using dco_out as feedback
but these are the warnings i got---

WARNING:Xst:2179 - "adpll.v" line -1: Specify blocks are ignored for synthesis.
WARNING:Xst:646 - Signal <CONT1> is assigned but never used.
WARNING:Xst:2170 - Unit adpll : the following signal(s) form a combinatorial loop: dco_out.

 

[shitansh]

Re: feedback input

hi,

upload div_10 .v file or if possible all .v files.

I am sure problem is with in div_10 .v file.

--
Shitansh Vaghela

 

[jadedfox]

Re: feedback input

hi,

upload div_10 .v file or if possible all .v files.

I am sure problem is with in div_10 .v file.

--
Shitansh Vaghela

The module i posted earlier is the top module.
Here's the rest of the part.....

//////////////div_10/////////////
module div_10( enable, in, out );
	input enable, in;
	output out;

	reg out;
	reg [3:0] cntr;
	
	
	initial
	begin
	 cntr <= 4'b0000;
	end
	
	always @( posedge in )
	begin
	if( !enable ) cntr <= 4'b0000;
	else if( cntr == 4'b1010 ) cntr <= 4'b0000;
	else cntr <= cntr + 1;
	end
	
	always @ ( posedge in )begin
	if( !enable ) out <= 1'b0;
	else if( cntr <= 4'b0100 ) out <= 1'b0;
	else out <= 1'b1;
	end
	
endmodule
//////////////////////////////////////////
/////////PFD////////////////////////
module pfd(  u1, u2, up, dn);
    input u1;
    input u2;
    output up;
    output dn;
	// output rst;
	 
	 //wire d = 1;
	 wire rst;
	 
	 d_ff D1 ( .d_in(1'b1), .clk(u1), .reset(rst), .d_out(up) );
	 d_ff D2 ( .d_in(1'b1), .clk(u2), .reset(rst), .d_out(dn) );
	 and ( rst, up, dn );
	 
endmodule

module d_ff ( d_in, clk, reset, d_out );
	input d_in;
	input clk;
	input reset;
	output d_out;
	
	reg d_out;
	
	
	always @ ( posedge reset or posedge clk )
	begin
	if (reset)
		d_out = 1'b0;
	else
		d_out = d_in;
	end
	
endmodule
///////////////////////////////////
/////controller///////////////////
module controller ( reset, clk, up, dn, DCO_CONTRL );
	input reset, up, dn, clk;
	output [7:0] DCO_CONTRL;
		
	reg freq_acq_mode, ph_acq_mode, step;
	reg [7:0] DCO_CONTRL;
	wire cond1, cond2, cond3, condp1, condp2;
	reg [7:0] cntf1, cntf2, cntp1, cntp2;
	reg [3:0] spd_cnt;
	reg [6:0] ss;
	reg [6:0] s_step;
assign cond1 = freq_acq_mode && step,
			 cond2 = freq_acq_mode && up,
			 cond3 = freq_acq_mode && dn,

			condp1 = ph_acq_mode && up,
		 condp2 = ph_acq_mode && dn;
			 
always @ (posedge clk )
begin

if (reset ) begin
		DCO_CONTRL <= 8'd127;
		ss <= 7'd64;
		freq_acq_mode <= 1;
		ph_acq_mode <= 0;
		cntf1 <= 0;
		cntf2 <= 0;
		step <= 0;
		end
		
else if (freq_acq_mode) begin
if (s_step == 1) step <= 1;

else step <= 0;

case ({cond1, cond2, cond3}) 

3'b100:begin 
		DCO_CONTRL <= DCO_CONTRL;
		s_step <= ss;
		freq_acq_mode <= 0;
		ph_acq_mode <= 1;
		cntf1 <= 0;
		cntf2 <= 0;
		end

3'b010:begin 
		freq_acq_mode <= 1;
		ph_acq_mode <= 0;
		cntf2 <= 0;
		cntf1 <= cntf1 + 1;
		DCO_CONTRL <= DCO_CONTRL + 1;
		s_step <= s_step;
		if (cntf1 <= 1) begin 
			s_step <= ss;
			s_step <= s_step / 2;
			ss <= s_step;
			end
		end

3'b001:begin 
		freq_acq_mode <= 1;
		ph_acq_mode <= 0;
		cntf2 <= cntf2 + 1;
		DCO_CONTRL <= DCO_CONTRL - 1;
		cntf1 <= 0;
		s_step <= s_step;
		if (cntf2 <= 1) begin
			s_step <= ss;
			s_step <= s_step / 2;
			ss <= s_step;
			end
		end
		
default: begin
			DCO_CONTRL <= 0;
			s_step <= s_step;
			cntf1 <= 0;
			cntf2 <= 0;
			freq_acq_mode <= 1;
			ph_acq_mode <= 0;
			end
endcase

end


else if (ph_acq_mode) begin

case ( {condp1, condp2} )
2'b10:
	begin 
		cntp2 <= 0;
		if (cntp1 > 1) begin
			cntp1 <= cntp1 + 1;
			spd_cnt <= spd_cnt + 1;
			s_step <= s_step;
			if (spd_cnt == 8) begin
				s_step <= s_step * 2;
				spd_cnt <= 0;
				cntp1 <= 0;
				end
			end
		else begin  
			cntp2 <= 0;
			s_step <= s_step;
			if (s_step != 1) s_step <= s_step / 2;
			cntp1 <= cntp1 + 1;
			spd_cnt <= spd_cnt + 1;
			end
		end
	
	
2'b01:begin 
		cntp1 <= 0;
		if (cntp2 > 1) begin 
			cntp2 <= cntp2 + 1;
			spd_cnt <= spd_cnt + 1;
			s_step <= s_step;
			if (spd_cnt == 8) begin
				s_step <= s_step * 2;
				spd_cnt <= 0;
				cntp2 <= 0;
			end
		end
		else begin 
			cntp1 <= 0;
			s_step <= s_step;
			if (s_step != 1) s_step <= s_step / 2;
			cntp2 <= cntp2 + 1;
			spd_cnt <= spd_cnt + 1;
		end
	end
default : begin
			cntp1 <= 0;
			cntp2 <= 0;
			s_step <= 0;
			spd_cnt <= 0;
			end
endcase

end
end

endmodule
//////////////////////////////////
/////dig_cntrl_osc/////////////

module dig_cntrl_osc ( enable, DCO_CONTRL, DCO_OUT );
	input enable;
	input [7:0] DCO_CONTRL;
	output DCO_OUT;
	
	wire cell4_out, cell3_out, cell2_out;
	//assign cell4in = DCO_OUTB;///
	not invsel0( CONTRL6b, DCO_CONTRL[6] );
	not invsel1( CONTRL7b, DCO_CONTRL[7] );
	and andsel0( sel0, CONTRL7b, CONTRL6b );
	and andsel1( sel1, CONTRL7b, DCO_CONTRL[6] );
	and andsel2( sel2, DCO_CONTRL[7], CONTRL6b );
	and andsel3( sel3, DCO_CONTRL[7], DCO_CONTRL[6] );
	nand nandout( DCO_OUTB, cell1_out, enable );
	not INV1( DCO_OUT1B, DCO_OUTB );
	not INV3( DCO_OUT, DCO_OUTB );
	not INV2( DCO_OUT2B, DCO_OUTB );

	
	assign cell4_in = sel0 ? DCO_OUTB : 1'b0;
	assign cell3_in = sel1 ? DCO_OUT2B : cell4_out;
	assign cell2_in = sel2 ? DCO_OUT : cell3_out;
	assign cell1_in = sel3 ? DCO_OUT1B : cell2_out;
	

	DCO_CELL cell1( DCO_CONTRL[5:0], cell1_in, cell1_out );
	DCO_CELL cell2( DCO_CONTRL[5:0], cell2_in, cell2_out );
	DCO_CELL cell3( DCO_CONTRL[5:0], cell3_in, cell3_out );
	DCO_CELL cell4( DCO_CONTRL[5:0], cell4_in, cell4_out );
	
endmodule
/////////////////////////////////